Browse Prior Art Database

METHOD AND ALGORITHM FOR FAST PARALLEL PROGRAMMING OF FLASH EEPROM

IP.com Disclosure Number: IPCOM000009171D
Original Publication Date: 1999-Jun-01
Included in the Prior Art Database: 2002-Aug-12
Document File: 1 page(s) / 58K

Publishing Venue

Motorola

Related People

Roberto Frontera: AUTHOR [+3]

Abstract

Flash EEPROM arrays are growing in array size with linear scalingof test time. A flash array has control registers associated for programingand eras- ing, and an external program/erase voltage pin. A flash array requires a program algorithm using these registers. For multiple flash arrays on a chip, the program algorithm has to be repeated for each dif- ferent array and control register locations, thus increasing software time during test. Also mutiple voltage pins are required unless the pin current can be controlled to provide enough current for each flash array.

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Developments Technical 0 M MOTOROLA

METHOD AND ALGORITHM FOR FAST PARALLEL PROGRAMMING OF FLASH EEPROM

by Roberto Frontera, Brian Crow and Shawn Cleary

   Flash EEPROM arrays are growing in array size with linear scalingof test time. A flash array has control registers associated for programingand eras- ing, and an external program/erase voltage pin. A flash array requires a program algorithm using these registers. For multiple flash arrays on a chip, the program algorithm has to be repeated for each dif- ferent array and control register locations, thus increasing software time during test. Also mutiple voltage pins are required unless the pin current can be controlled to provide enough current for each flash array.

   A hardware and software method is required to reduce the growth rate of test time required for large flash EEPROM arrays. The Fast Parallel Programming (FPP) method uses existing hardware designs and realigns the hardware array locations as well as the control registers with minimal hard- ware added.

   The FPP method requires one control bit, ROMTST, that is only written during test modes. When ROMTST bit is set, FPP is enabled and all

flash arrays have same map equation through hard- ware decode during write access, yielding parallel write access to array locations. Similarly, the memo- ry map equations for the control registers are shared so that multiple flash registers can be accessed in single parallel write cycles. Read cycles are never performed in...