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Interconnect Routing Structure of Stacked FBGA Package Design Enabling Reduction of Parasitic Inductance in Conductive Traces

IP.com Disclosure Number: IPCOM000009238D
Original Publication Date: 2002-Sep-25
Included in the Prior Art Database: 2002-Sep-25
Document File: 2 page(s) / 255K

Publishing Venue

Siemens

Related People

Juergen Carstens: SUBMITTER

Abstract

Stacked FBGA (Fine-pitch Ball Grid Array) memory technology is an attractive solution in cases when a high memory density is required. Single chip solutions are not yet available or have low yield and high costs. However, the electrical performance of stacking solutions must not break system timings. Although FBGA packages have low parasitics, they hold up to 50% of signal line inductances. The overall conductor line inductance for stacked solutions may become critical, as well as inductance matching for bottom and upper chip signal paths. Generally there is an inductance mismatch, espe-cially in the case of over-the-edge stacking solutions, where a z-axis connection over the chip is re-quired (figure 1). The signal line from the upper chip starts from the pad row, that is centered in the middle of the mem-ory chip, and ends at the package ball (figure 2), often by a redistribution layer routed onto the chip surface (figure 3). The upper chip interconnect may have inductances up to 9nH depending on the design type and chip size. The issue may not allow the usage of the stacking solution at high clock frequencies. Up to now there are two ways to reduce inductances in stacked package designs:  shorten the signal path to the upper chip by thinner chips and shorter wirebonds  adding separate ground planes where possible However, these solutions add design and manufacturing costs which are undesirable for low-cost, high-volume memory production. That’s why “comb-like” routing of VSS traces between the signal traces is proposed (figure 4). These ground traces act as a current return path for the signal trace. VSS signal path is shaped as a ring over the chip edge and from this ring is routed among signal traces with a minimum pitch. Signal traces of the redistribution layer should be made as wide as possible to decrease inductance as well. The same routing can be done on the FBGA substrate, when the substrate is at least double-sided and offers place for routing VSS traces among the signal ones. The advantages of the proposed method are:  no additional metal layers required  low cost solution  good inductance matching for upper and lower chip in FBGA stacking solution  reduces mutual inductances between signal traces

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Interconnect Routing Structure of Stacked FBGA Package Design Enabling Reduction of Parasitic Inductance in Conductive Traces

Idea: Dr. Jochen Thomas, DE-München; Dr. Minka Gospodinova, DE-München

Stacked FBGA (Fine-pitch Ball Grid Array) memory technology is an attractive solution in cases when a high memory density is required. Single chip solutions are not yet available or have low yield and high costs. However, the electrical performance of stacking solutions must not break system timings. Although FBGA packages have low parasitics, they hold up to 50% of signal line inductances. The overall conductor line inductance for stacked solutions may become critical, as well as inductance matching for bottom and upper chip signal paths. Generally there is an inductance mismatch, espe- cially in the case of over-the-edge stacking solutions, where a z-axis connection over the chip is re- quired (figure 1).

The signal line from the upper chip starts from the pad row, that is centered in the middle of the mem- ory chip, and ends at the package ball (figure 2), often by a redistribution layer routed onto the chip surface (figure 3). The upper chip interconnect may have inductances up to 9nH depending on the design type and chip size. The issue may not allow the usage of the stacking solution at high clock frequencies.

Up to now there are two ways to reduce inductances in stacked package designs:

[g183] shorten the signal path to the upper chip by thinner chips and shorter...