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Method for a parallel compare-select-add unit

IP.com Disclosure Number: IPCOM000009250D
Publication Date: 2002-Aug-13
Document File: 4 page(s) / 79K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a parallel compare-select-add (PCSA) unit. Benefits include improved performance.

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Method for a parallel compare-select-add unit

Disclosed is a method for a parallel compare-select-add (PCSA) unit. Benefits include improved performance.

Background

              Wireless communications, including wireless local area networks and cellular phones, are subject to impairments such as noise, cochannel interference, and multipath fading. Forward error correction (FEC) coding is a method of adding redundancy to the transmitted data so that the receiver can recover the original information bits.

              Some popular methods of FEC coding include block, convolutional, and more recently, turbo codes. The transmitter includes an encoder that adds redundant data to the original information. After encoding, all of the bits are modulated and transmitted over a noisy link to the receiver. The receiver includes the corresponding decoding algorithm that uses the redundant information to reconstruct the original bits that were transmitted.

              One popular method of FEC coding uses a convolutional code and a Viterbi decoder. The Viterbi decoder processes the received, noisy symbols and finds the most likely transmitted sequence. The Viterbi decoder is very computationally intensive and its complexity is related exponentially to the length of the convolutional encoder.

              The communications equipment designer is faced with conflicting demands. In general, there is an increasing demand for higher bandwidth communications to accommodate the user’s desires to transmit and receive multimedia, such as digital video and television. Higher data rates usually mean higher cost, power consumption, and size. On the other hand, a requirement exists to minimize the power consumption, cost, and size of the communications equipment. Another requirement exists to reuse conventional technology to reduce the time to market for communications equipment.

              The most computation demanding operation of the Viterbi decoder is the state-update phase. In it, all possible states of the encoder’s state-machine and all possible input values to the encoder are checked to identify the most probable transition. The end goal is to identify the flow of states through which the encoder has passed through while encoding the input stream. Identifying this flow enables the reconstruction of the input stream in the receiver.

              The state-update phase of the Viterbi decoder uses accumulators to track the probability for each one of the possible flows in the encoder’s state-machine (the number of accumulators matching the number of states in the encoder’s state machine).

              In the encoder, a single bit entering the encoder causes a single transition of the state-machine (for example, a transition from one state, Ssrc, to another, Sdst). As part of this transition, the encoder outputs two or more bits. The Viterbi decoder checks all the states that can reach state Sdst and decides which transition is the most probable. Due to the encoder’s str...