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Method for a NAND-fill test chip

IP.com Disclosure Number: IPCOM000009252D
Publication Date: 2002-Aug-13
Document File: 6 page(s) / 122K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a NAND-fill test chip. Benefits include an improved test environment.

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Method for a NAND-fill test chip

Disclosed is a method for a NAND-fill test chip. Benefits include an improved test environment.

Background

              Conventionally, defect density information is gathered either by a static random-access memory (SRAM) array or by testing the lead product on a new process. Typically, the SRAM array is comprised of a repeating pattern that does not have the same metal spacing, density, and general layout style of a random logic product. Therefore, the results may not provide an accurate representation of the defect density of the product. The lead product typically uses a test tool to isolate defects, which has historically provided poor spatial resolution. Sometimes the resolution is only to within 10s of nodes, and sometimes it stretches over a very large area of the chip. Furthermore, the product requires complex post-processing of the test data to isolate the failing node.

General description

              The disclosed method is a NAND-fill die that is designed with the same metal design rules and layout style as a random logic process to provide the defect location to within a small number of nodes (typically, 2). The method also immediately identifies the failing node and the node’s metal layer with only simple post-processing of the test data.

Advantages

              The disclosed method provides advantages, including an improved test environment due to the design of the NAND-fill chip.

Detailed description

              The core of the NAND-fill die is the NAND-fill array, which consists of one NAND-chain for each metal and via layer in the fabrication process. Each NAND chain is routed exclusively in its target layer. Metal shorts or opens and via opens are detected when a test signal fails to propagate through the NAND chain in the quick-check mode. The defect can be further isolated in the scan mode.

              In the schematic and simplified truth table for the NAND-fill cell, when both the row and column signals are low, the cell blocks the input signal and the output is high (see Figure 1). When either the row or column is high, the cell effectively becomes an inverter, and the output is driven to the inverse of the input.

              In single layer quick-check mode, all of the row signals are driven high, and all of the NAND-fill cells in the array act as inverters (see Figure 2). The input of the array is toggled from low to high, and the output of the array should likewise toggle from high to low. If the output remains either high or low, then a defect exists somewhere in...