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Method for a die bump structure and improved chip joint yield and package reliability

IP.com Disclosure Number: IPCOM000009290D
Publication Date: 2002-Aug-14
Document File: 4 page(s) / 76K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a die bump structure and improved chip joint yield and package reliability. Benefits include improved yield, improved reliability, improved development, and improved support for future processes.

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Method for a die bump structure and improved chip joint yield and package reliability

Disclosed is a method for a die bump structure and improved chip joint yield and package reliability. Benefits include improved yield, improved reliability, improved development, and improved support for future processes.

Background

        � � � � � The non-wet (no inter-metallic layer is formed between die bump and substrate bump during reflow process) is one of the major yield loss contributors, and solder joint fatigue failure is one of the major reliability issues in flip-chip technology. These two concerns are intensified with no-flow underfill technology because the fluxing capability of no-flow materials is typically poorer than the process of record (POR) flux stage. Most conventional no-flow materials are not silica filled and have a relatively high coefficient for thermal expansion (CTE).

        � � � � � The non-wet condition is conventionally improved through optimizing the chip attach process and no-flow formulations. However, the improvement window is narrow due to the weaker fluxing capability nature compared to conventional flux.�

        � � � � � Solder joint reliability is improved through underfill material improvement, such as using lower CTE material and/or changing the bump metallurgy. These methods require long development time and high cost.

General description

� � � � � The disclosed method is a flip-chip die bump structure using a two-step or multi-step electroplating process and/or a screen-printing process in which the first step is a conventional Cu column-bumping process. Subsequent steps build smaller Cu column bumps or other required metallurgy bumps with controlled shape. This die bump structure improves the non-wet yield loss (especially for no-flow underfill technology) and enhances solder joint reliability.� � � �

� � � � � The key elements of the method include:

·        Die bump structure that consists of a bottom bump with a larger diameter and a top bump with a smaller diameter

·        Shape and metallurgy of the smaller-diameter top bump�

·        Process of fabricating the die bump structure

 


Advantages

        � � � � � The disclosed method provides advantages, including:

·        Improved yield and reliability due to reduction of the non-wet condition

·        Improved reliability due to reduction of solder joint fatigue failure

·        Improved reliability due to the extension of the top part of the die bump into the substrate solder, which effectively changes...