Browse Prior Art Database

Improved Electromigration Resistance of Copper Interconnects using Multiple Cladding Layers

IP.com Disclosure Number: IPCOM000009315D
Original Publication Date: 2002-Aug-15
Included in the Prior Art Database: 2002-Aug-15
Document File: 3 page(s) / 422K

Publishing Venue

Motorola

Related People

James Walls: AUTHOR [+6]

Abstract

With the advent of more advanced generations of complementary metal oxide semiconductor (CMOS) technology, the demands for performance, particularly operating current density, continue to increase. These demands for increased current density directly translates into a demand for increased interconnect electromigration (EM) resistance. We have discovered that certain schemes of interconnect cladding, using multiple layers of Ta and NiFe, lead to an improved EM performance. Although cladding was originally developed as a flux concentrator in magnetoresistive random access memory (MRAM) technologies, it can be used to improve the EM performance even in interconnect levels and/or technologies that do not require cladding.

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Improved Electromigration Resistance of Copper Interconnects using Multiple Cladding Layers

James Walls, Mark Durlam, Donald Gajewski, Taehoon Kim, Matt Martin, Douglas Qualls

With the advent of more advanced generations of complementary metal oxide semiconductor (CMOS) technology, the demands for performance, particularly operating current density, continue to increase. These demands for increased current density directly translates into a demand for increased interconnect electromigration (EM) resistance. We have discovered that certain schemes of interconnect cladding, using multiple layers of Ta and NiFe, lead to an improved EM performance. Although cladding was originally developed as a flux concentrator in magnetoresistive random access memory (MRAM) technologies, it can be used to improve the EM performance even in interconnect levels and/or technologies that do not require cladding.

A critical issue in advanced CMOS technology development is the interconnect intrinsic reliability performance or resistance to electromigration (EM). Subsequently more advanced generations of CMOS technology feature decreased critical dimensions, and many new products require increased performance requirements, including current density, particularly in high-current applications such as magnetoresistive random access memory (MRAM). Both of these factors lead to increasing current density requirements, and hence increasing demands for interconnect EM resistance.

Our solution is to improve the EM performance by introducing a combination of barrier and cladding layers surrounding the interconnects. This solution can improve the EM performance by altering one or more of the following physical characteristics of the interconnects and their environment: (1) interface energies, (2) surface diffusion activation energies, (3) interconnect microstructure, or (4) some other mechanism yet to be determined. This solution is unique because it has identified certain combinations of cladding and...