Browse Prior Art Database

EFFICIENT BUILT-IN MEMORY CHECK METHOD

IP.com Disclosure Number: IPCOM000009341D
Original Publication Date: 1999-Jun-01
Included in the Prior Art Database: 2002-Aug-19
Document File: 4 page(s) / 224K

Publishing Venue

Motorola

Related People

Ezzy Dabbish: AUTHOR [+3]

Abstract

This circuit describes the use of a software/hard- ware accessible memory check circuit that can be used to verify program memory integrity prior to critical operations. The use of the existing Jump-to- Subroutine (JSR) instruction with a special address trap starts the checking process. The checking process passes the contents of the program memory followed by its CRC into a CRC circuit yielding a constant answer which can be easily checked by a simple hardware comparator. The checking process ends by invoking a Return-from-Subroutine (RTS) instruction that returns control to the main program. All of these elements result in an efficient and low cost solution.

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MOTOROLA Technical Developments

  EFFICIENT BUILT-IN ~ MEMORY CHECK METHOD

by Ezzy Dabbish, Tom Messerges and Greg Baie

ABSTRACT

  This circuit describes the use of a software/hard- ware accessible memory check circuit that can be used to verify program memory integrity prior to critical operations. The use of the existing Jump-to- Subroutine (JSR) instruction with a special address trap starts the checking process. The checking process passes the contents of the program memory followed by its CRC into a CRC circuit yielding a constant answer which can be easily checked by a simple hardware comparator. The checking process ends by invoking a Return-from-Subroutine (RTS) instruction that returns control to the main program. All of these elements result in an efficient and low cost solution.

INTRODUCTION

  Many situations require a microprocessor to self-check its operation before performing critical system functions. Such critical functions might include banking transactions, transmission of encrypted data, military applications or law enforce- ment applications. Typical microprocessors retrieve instructions from memory and proceed to execute them; however, if the instruction memory has been corrupted, then the instructions being executed may contain errors. The execution of these invalid instructions may compromise the system security and integrity. This is critical for a microcontroller that contains non-volatile memory such as EPROM, EEPROM or flash EEPROM, that are potentially subject to losing their memory contents over time or due to malfunction.

  In systems which critical functions are being performed and speed of operation is vital, special hardware can be used to verify proper operation. One solution might be to add a parity bit(s) to each memory word, thus safeguarding against various types of data loss and ensuring instruction validity.

The main problem with such a solution is that the extra memory required td store parity bits depends on the total size of the i&truction memory and can become quite. expensive. Thus, a solution that con- serves memory and dyna$ically protects against the execution of invalid instnictions is needed.

DESCRIPTION

  The technique described in this paper verifies instruction integrity with 'special hardware that cal- culates a CRC on the program memory. Using this approach, a single location is used to store a CRC for the entire memory, rather than parity bits for every location. The main advantage of such a tech- nique is the memory saved by consolidating the CRC check bits into a single word and also the speed at which the overall critical task instructions can be executed is potentially increased. The block diagram in Figure 1 illustrates how the memory check circuit would interface with a typical micro- processor.

  Prior to commencing: a "critical" operation, the CRC hardware is initialized and proceeds to calcu- late a CRC over the pro4am memory. Instructions are sequentially retrieved from the pro...