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BUS INTERFACE TERMINATION PROTOCOL FOR LOW POWER SYSTEMS

IP.com Disclosure Number: IPCOM000009342D
Original Publication Date: 1999-Jun-01
Included in the Prior Art Database: 2002-Aug-19
Document File: 3 page(s) / 125K

Publishing Venue

Motorola

Related People

Bill Moyer: AUTHOR

Abstract

Low power CMOS systems rely on a number of power saving design techniques to reduce overall system power consumption. Notably, reduced sig- nal swing (voltage component) and reduction of sig- nal switching activity (effective switching frequency component) are among the most effective tech- niques for power reduction in a traditional CMOS design.

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Developments T~chnicul 0 M MOlOROLA

BUS INTERFACE TERMINATION PROTOCOL FOR LOW POWER SYSTEMS

by Bill Moyer

  Low power CMOS systems rely on a number of power saving design techniques to reduce overall system power consumption. Notably, reduced sig- nal swing (voltage component) and reduction of sig- nal switching activity (effective switching frequency component) are among the most effective tech- niques for power reduction in a traditional CMOS design.

  In a low power single chip system consisting of a processor (CPU), one or more memories (ROM, RAM, FLASH), and a set of peripherals (GPIO, SPI, UART, etc.) are interfaced together via a shared address bus, data bus and control bus. The effective switching activity on elements of the control bus is addressed herein.

The Motorola M*CORE's bus interface requires

labeled TERMCTL. Since them and TEA signals are shared by all internal blocks, thus they must be driven in a coordinated manner.

  In order to reduce transitions on the TA line, a single unit, the TERMCTL unit is made responsible for the negation of the -A and TEA signals, while several units may assert these signals. This allows a reduced capacitance on the m and TEA signals since pullup (P type) transistors are not used except by the TERMCTL block.

  In the system shown, :since the termination tim- ing for the RAM and ROM are deterministic (0 wait states), assertion of m for these two blocks may also be handled by the TERMCTL unit. In an alter- nate system which includes a cache memory, a nat- ural place for this function to exist would be as part of the Cache Logic, since single cycle hit/miss determination will need to cause the TA signal to negate or remain asserted for consecutive cache accesses. As long as consecutive accesses are to a RAM or ROM location,...