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A 1.2V 10UA SINGLE-ENDED LOW POWER COMPACT SENSE AMP FOR HIGH DENSITY LOW VOLTAGE FLASH MEMORIES

IP.com Disclosure Number: IPCOM000009348D
Original Publication Date: 1999-Jun-01
Included in the Prior Art Database: 2002-Aug-19
Document File: 5 page(s) / 218K

Publishing Venue

Motorola

Related People

Shayan Zhang: AUTHOR [+2]

Abstract

It is unavoidable in high density flash memory design to use a low voltage low current sensing scheme with minimum bitline on-pitch selection cir- cuit as the flash technology continues to scale down and the memory size increases. This is because 1) the bitcell current is reduced in line with the finer pitch while the bitline capacitance is increased; 2) the performance gain by scaling is limited by the tight layout pitch of peripheral circuitry; 3) dynami- cally sensing schemes impose a speed limit by adding periods of precharging operations. The fol- lowing sections describe a new approach to address these problems: (a) The new circuit shown in Figure 1 achieves data sensing at relatively high speed with relatively low power consumption, by utilizing a static current sense amplifier and eliminating precharge periods required for dynamic sensing schemes, unlike prior art using direct voltage sensing with one or more bitline precharge and/or discharge phases (s= HI, PI).

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Page 1 of 5

MOTOROLA Techical Developments

A 1.2V IOUA SINGLE-ENDED LOW POWER COMPACT SENSE AMP FOR HIGH DENSITY LOW VOLTAGE FLASH MEMORIES

by Shayan Zhang and Vern Meyer

INTRODUCTION

  It is unavoidable in high density flash memory design to use a low voltage low current sensing scheme with minimum bitline on-pitch selection cir- cuit as the flash technology continues to scale down and the memory size increases. This is because 1) the bitcell current is reduced in line with the finer pitch while the bitline capacitance is increased; 2) the performance gain by scaling is limited by the tight layout pitch of peripheral circuitry; 3) dynami- cally sensing schemes impose a speed limit by adding periods of precharging operations. The fol- lowing sections describe a new approach to address these problems:

  (a) The new circuit shown in Figure 1 achieves data sensing at relatively high speed with relatively low power consumption, by utilizing a static current sense amplifier and eliminating precharge periods required for dynamic sensing schemes, unlike prior art using direct voltage sensing with one or more bitline precharge and/or discharge phases (s= HI, PI).

  (b) The circuit minimizes the overhead of bit- line on-pitch selection circuitry by using only one low voltage Nh4OS transistor at short gate length. Together with the simple structure of the sense amp,

page read mode architecture can be realized. Prior art generally requires at least 3 transistors per bitline pitch to achieve low voltage operation, e.g. a full- CMOS transmission gate plus bitline loading ele- ments.

  (c) The circuit enables operation with power supply voltages as low as 1.0.volt and sensing cur- rent as low as 1kA by operating memory bit cells only in the linear region so that the bitline voltage disturbance and source line current disturbance problems are eliminated. Operating bitcells in the linear region makes the sense operation less sensi- tive to variations of bitcell characteristics, caused by process variations, device scaling down, and device aging, than that in the saturation region.

  (d) The data sensing speed is insensitive to process dependent bitline capacitance and dataline routing capacitance by clamping the bitline and dataline voltage to a fraction of V, (- 0.3V). This relaxed the difficulties of speed reduction for high density flash memories with finer pitch where, in general, the memory cell current is reduced while the bitline capacitance is increased.

  The concept of this low current sense amp has been verified with a 1M flash memory test chip.

0 Mcanmla.lnc. ,999 251 June 1999

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MOTOROLA Technical Developments

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Fig. 1 New Sense Amp and Decode Structure

Sense Amp & PGM Latch

DESCRIPTION

   In the sense amp and decode structure, illust...