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METHOD AND APPARATUS TO ALLOW A CIRCUIT IN A LOW VOLTAGE PROCESS ACCEPT A HIGH VOLTAGE INPUT

IP.com Disclosure Number: IPCOM000009349D
Original Publication Date: 1999-Jun-01
Included in the Prior Art Database: 2002-Aug-19
Document File: 4 page(s) / 147K

Publishing Venue

Motorola

Related People

Joseph Chan: AUTHOR [+3]

Abstract

Current trends in VLSI processing is pushing towards the use of lower on chip power supplies. For example: the evolution from a UDR75 (150 A gate oxide) to the CDRl (9OA gate oxide), or CDR2 (70 A gate oxide) process has forced us to go from a 5V supply to a 3V supply. Eventually when the gate oxide reaches the 20A range the maximum on chip supply will be 0.9V.

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MOlOROLA @ Technical Developments

METHOD AND APPARATUS TO ALLOW A ClRCblT IN A LOW VOLTAGE PROCESS ACCEPT A HIGH VOLTAGE INPUT

by Joseph Chan, Marc Tarabbia and Juan Buxb

INTRODUCTION

  Current trends in VLSI processing is pushing towards the use of lower on chip power supplies. For example: the evolution from a UDR75 (150 A gate oxide) to the CDRl (9OA gate oxide), or CDR2 (70 A gate oxide) process has forced us to go from a 5V supply to a 3V supply. Eventually when the gate oxide reaches the 20A range the maximum on chip supply will be 0.9V.

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  However the power svpply of some applications cannot follow this rapid wend in supply reduction. We are now faced with jhe problem of having to interface a low voltage (WDL) circuit to a higher voltage (VDDH) circuit on the application board. Even if we can have mukple supplies on the board, the low voltage (e.g. 3V) circuit will still have to be able to accept an input voltage (e.g. 5V) much high- er than what its gate ox&e can withstand reliably. Oxide breakdown becomes a serious problem here. Figure 1 briefly illustrates the above described con- figuration.

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Developments Technical 0 M MOTOROLA

HIGH VOLTAGE TO LOW VOLTAGE INTERFACE

  In order to be able to operate correctly without any degradation in reliability the circuits designed in a low voltage process, and having to accept a high voltage input, will need to have a built in high volt- age to low voltage interface.

  Prior art solutions to implement such interfaces include the use of a thick oxide gate at the input; i.e. the use of a dual oxide gate process. Such a process is more complex than the baseline logic process and involves at least three extra masks. The dual oxide

gate process is more expensive and thus makes the global chip less competitive.

  Our invention is an efficient high voltage to low voltage interface that does not require the use of dual oxide gate process. This interface coupled with a low voltage input buffer gives us a very good high voltage to low voltage input buffer using only the baseline logic process. This represents an enormous advantage to the digital circuit using it.

  A general schematic diagram of the invention is shown in Figure 2 below.

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Fig. 2 General Implementation of Invention Using i...