Browse Prior Art Database

Distributed Process for Large Layout Hierarchy Management

IP.com Disclosure Number: IPCOM000009375D
Publication Date: 2002-Aug-20
Document File: 8 page(s) / 100K

Publishing Venue

The IP.com Prior Art Database

Abstract

Distributed processing approaches for handling large integrated circuit layouts are described. By paralellizing the process and further by interleaving set up (recognition of instances that need processing) with the processing (e.g. optical proximity correction, phase shifting design, etc.) large speed improvements can be achieved.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 50% of the total text.

Page 1 of 8

1. Descriptive Title

Distributed process for large layout hierarchy management

2. Problem

Parallel processing, either multi-thread or distributed process, has been used wildly in optical proximity effect corrections (OPC) and simulation based verification. However, such applications have not been applied to the entire process that consists hierarchical management and simulation. The hierarchical management is still a single machine operation and the simulation correction process has been running over multiple machines. As the file size continue to increase, a large layout (>2GB) handling becomes a issue due to memory consumption and performance. . If the input layout is around 2GB then the image of the layout in memory could be more than 16GB. This huge memory usage could lead to crash in 32bit executable or significant slow down in 64bit.

3. Solution

To handle a huge layout it's better to follow the rule "divide and conquer". If the layout is split into smaller pieces then the memory requirement for each of the pieces would be much smaller than the whole layout, and the hierarchy management can run in parallel for each pieces. This new approach consists 3 steps: 1. simple rule based split on a single machine, 2. complicated hierarchy managements on multiple machines, 3. comprehensive simulations on multiple machines for each split. The way to split the layout could fall into following 3 categories.
1.split in chess board sytle : this method will split the layout into rectangles. Each of the pieces will contain the geometries and the hierarchy that fall into the grid.
2. split based on user coordinates : this will split the layout based on the user input coordinates. The method ensures more efficient hierarchy processing if the split is based on the separate module in the layout.
3. split based on gaps : Trace the gap between the geometries and split independent modules of the layout. After the split we could run PipeDP for each of the layout with the help of IB. The IB can generate common instances of cells. Whenever IB generates instances PipeDP will distributed them to processors waiting for jobs. After all the instances are processed PipeDP will merge the processed instances and original layout to produce output layout. Once we have the processed...