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Method for saving power for current mirror DACs

IP.com Disclosure Number: IPCOM000009377D
Publication Date: 2002-Aug-20
Document File: 6 page(s) / 113K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for saving power for current mirror digital-to-analog converters (DACs). Benefits include improved power consumption and improved design simplification.

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Method for saving power for current mirror DACs

Disclosed is a method for saving power for current mirror digital-to-analog converters (DACs). Benefits include improved power consumption and improved design simplification.

Background

              The conventional, simple CMOS current mirror DAC includes a MOS current source cell, i13, which switches on and off to toggle 1-bit of current (see Figure 1). An 8-bit DAC requires 256 current cells. Resistor i2 is utilized for I-V translation when driving a capacitive load. Note that the schematic of the MOS current cell is only a conceptual one. A practical implementation is typically more complex, such as using a differential current switch and compensation circuitry.

Current mirroring is a conventional method used in CMOS DAC implementation. Many variations are used in designing the MOS current cells (such as hierarchy organization and device matching). All of them use one of the following two methods as output stage and translate the current (I) into voltage (V):

·        Use a current mode output and use the load resistor to generate the analog voltage (see Figure 2). This solution is the simplest design and is typically used in high-speed, low voltage, low current, fixed (well matched) load-resistance (50-ohm) applications, such as video DACs. However, this method cannot handle capacitive load.

·        The most common output stage for CMOS current mirror DAC is an opamp buffer (see Figure 3). The current cells are sized as small as possible so that DC power is low. The opamp is used to drive large loads. However, when the load is a large capacitor (>1 nf), designing the opamp with a super-fast slew rate and meeting stability (phase margin) requirements is very difficult. 

Description


              The disclosed method is a circuit technique that saves power consumption while maintaining full speed and the dynamic range of CMOS current mirror DACs. While the current-cell design is not included within the scope of the disclosed method, the voltage-setting resistor, i2, is included.
              To achieve maximum speed, resistor i2 must be as small as possible to obtain maximum charging current. However, after the load reaches the required value, the DC current through resistor i2 and the MOS transistors must be kept at minimum. The level is just high enough to overcome noise disturbance on the output voltage. The disclosed method includes a resistance multiplication network that achieves this requirement (see Figure 4). A 7-bit DAC contains 128 MOS curr...