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Bandwidth Throttling for SDR/DDR Main Memory

IP.com Disclosure Number: IPCOM000009386D
Publication Date: 2002-Aug-20
Document File: 2 page(s) / 41K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that limits bandwidth (BW) consumed by the chipset or DRAM over a programmable period of time. Benefits include the protection of DRAMs from thermal damage.

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Bandwidth Throttling for SDR/DDR Main Memory

Disclosed is a method that limits bandwidth (BW) consumed by the chipset or DRAM over a programmable period of time. Benefits include the protection of DRAMs from

thermal damage.

Background

DRAM devices and chipsets generate heat while performing read or write operations.� Depending on a variety of factors, it is possible for a chipset or DRAM device to overheat from too much activity. Currently, chipsets do not implement throttling on a per row basis, and also do not implement the mechanisms of the Global DRAM Sampling Window (GDSW).

General Description

The disclosed method used the DRAM controller to measure the BW of each row of memory independently, and compares each against a programmable limit. It also measures the BW of the chipset and compares it against a different programmable limit. When the BW is exceeded, we enter the throttling mode.

The BW is measured over a programmable GDSW. If the BW exceeds the programmed limit, we enter throttling mode for the remainder of the current GDSW and all of the next GDSW.� The BW allowed for the remainder of the current GDSW and all of the next (after we have entered throttling mode) depends on where in the GDSW we exceeded the BW (the later in the GDSW, the lower the BW). After the second GDSW, the throttling mode exits and measuring the BW consumed begins again (see Figure 1).

When measuring the BW consumed by the DRAM rows both read and writes are included, because the power consum...