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DQS Timing Calibration Based on High-Speed Capture of a Deterministic Data Pattern

IP.com Disclosure Number: IPCOM000009387D
Publication Date: 2002-Aug-20
Document File: 2 page(s) / 112K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that improves Dual Data Rate SDRAM (DDR) read operations with a process that detects data arrival in relation to the MCH memory core clock. Benefits include cost reductions and simplified read operations.

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DQS Timing Calibration Based on High-Speed Capture of a Deterministic Data Pattern

Disclosed is a method that improves Dual Data Rate SDRAM (DDR) read operations with a process that detects data arrival in relation to the MCH memory core clock. Benefits include cost reductions and simplified read operations.

Background

Currently, for DDR read operations, the Data Strobe (DQS) signal is calibrated to provide adequate setup and hold time for incoming read data. However, due to system uncertainty the data arrival time of the DQS strobes vary. In addition, the DQS signal is Stub Series Terminated Logic (SSTL), which can cause noise associated with the DQS signal to inadvertently change internal pointers; this requires that the Memory Controller Hub (MCH) input buffer is only turned during DQS reads.

General Description

The disclosed method uses the following procedure to detect data arrivals in relation to the MCH memory core clock (see Figures 1 and 2):

 

  1. Memory locations are written with either 0s or 1s.
  2. Back to Back reads are to memory locations written with 0s (Rd-0), followed by reads to memory locations written with 1s (Rd-1).
  3. The DQS input buffer is enabled during the data arrival.
  4. A shift register samples incoming DQ data on both the rising and falling edge of a high-speed internal clock.
  5. A data pattern change from Rd-0 to Rd-1 causes the capturing register to detect

a 0 to 1 shift.

  1. The capture signature is fed to a configuration register, and programmed when the DQS input...