Browse Prior Art Database

Scheme to Update Rcomp Values for DDR Buffers

IP.com Disclosure Number: IPCOM000009388D
Publication Date: 2002-Aug-20
Document File: 3 page(s) / 106K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that enables error-free Rcomp calibration for clocks and level-sensitive signals. The disclosed method can be used with all future DDR memory controller chip sets.

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Scheme to Update Rcomp Values for DDR Buffers

Disclosed is a method that enables error-free Rcomp calibration for clocks and level-sensitive signals. The disclosed method can be used with all future DDR memory controller chip sets.

Background

Rcomp dynamically tunes the IO buffers to account for variations in operating conditions due to process, temperature, voltage, and board layout. Compensation is required initially, when MCH is out of reset, and periodically during operation.

General Description

DDR buffers are divided into different groups based on functional requirements and loading (see Figure 1). Among the commands are: Chip Select (CS#), Clock Enable (CKE), Data and Strobe (DQ and DQS), Clocks (CK and CKB), and Receive Enable (RCVEN).

Updates are performed when the signals are idle. DQ, DQS, and CS#  groups are updated during the Ras cycle time. However, CK, CKB, CKE, and RCVEN are driven constantly and require updating without logically impacting the signal.

The CKE, CS#, and RCVEN groups are updated using the indirect Rcomp update mechanism (see Figure 2). In this mechanism, the update latches are held open for two clocks instead of one (direct update). During the first clock period, the maximum strength values are driven to the buffers. During the second clock period, the calibrated value is driven and latched in the IO buffers; this prevents signal errors.

The CK and CKB groups are updated using the synchronous update mechanism (see Figure 3). In this mechanism,...