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Programmable Turn-Around Time for Selected DRAM Cycles

IP.com Disclosure Number: IPCOM000009390D
Publication Date: 2002-Aug-20
Document File: 2 page(s) / 70K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for improving the turn-around time for selected DRAM cycles. Benefits include a flexible design that can accommodate various system configurations.

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Programmable Turn-Around Time for Selected DRAM Cycles

Disclosed is a method for improving the turn-around time for selected DRAM cycles. Benefits include a flexible design that can accommodate various system configurations.

Background

To avoid data corruption caused by multiple drivers working the same data bus, turn-around times are specified for DDR memory. These turn-around times may be affected by various system parameters. For example, a Read cycle follows a Write cycle, but the Read may be the furthest DIMM while the Write may be the closest DIMM; this difference in flight times affects the overall turn-around time on the bus. As a result of varying turn-around times, overestimating is implemented to avoid data corruption; however, overestimating affects performance because back-to-back cycles are issued more infrequently.

General Description

The disclosed method accounts for all possible system configurations and turn-around time variations. The disclosed method uses configuration registers to define the cycle spacing time required between two different requests (e.g. a Read followed by a Write). The GMCH cycle tracker machines program the appropriate cycle spacing time when the first cycle time is issued. The next cycle is issued only when the this programmed cycle spacing time is met, thereby regulating the turn-around time and preventing any bus collisions (see Figure 1).

Advantages

Some implementations of the disclosed structure and method provide one or more of...