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METHOD FOR TOLERATING SCHEDULING LATENCY IN HIGH SPEED MODEMS IMPLEMENTED ON HOST PROCESSORS

IP.com Disclosure Number: IPCOM000009408D
Original Publication Date: 1999-Sep-01
Included in the Prior Art Database: 2002-Aug-21
Document File: 6 page(s) / 255K

Publishing Venue

Motorola

Related People

Jian Yang: AUTHOR

Abstract

With host processors in personal computers becoming more and more powerful, it becomes fea- sible to implement high speed modems such as ADSL modems in software. However, computation complexity or mips is not the only challenge for a successful implementation of high speed modems. The DSP functions for the high speed modems require real-time execution. However, the host processor may be running many other tasks concur- rently such that its operating system may not be able to guarantee the timely execution of the real-time DSP functions, i.e. there is large response delay. If not being dealt properly, the large response delay can cause transmit buffer underflow and/or receive buffer overflow.

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MOTOROLA Technical Developments

8

METHOD FOR TOLERATING SCHEDULING LATENCY IN HIGH

SPEED MODEMS IMPLEMENTED ON HOST PROCESSORS

by Jian Yang

Buffer, which stores the A/D samples to be processed by the Rx DSP task, they are implement- ed in host memory. The TX and Rx tasks are execut- ed by the host processor and are scheduled by the host operating system task scheduler.

  A request is generated to the operating system, typically in the form of an interrupt, when the num- ber of samples in the TX buffer is below a threshold for an execution of the TX task. Similarly, a request for Rx task is generated when the number of sam- ples in the Rx buffer is above a threshold. As dis- cussed earlier, the OS scheduler may not be able to schedule the execution of the TX/RX task immedi- ately. The scheduling latency, as defined as the delay of actual execution of the task from the time when the request is generated, is very large. Clearly, if the latency exceeds the amount of time it takes to transmit the remaining samples in the TX buffer, we would have a TX buffer underrun prob- lem. Likewise, if the Rx task does not get executed by the time the Rx buffer is completely filled, we would have a Rx buffer overrun problem.

  In a host environment, although the worst case scheduling latency can be very large, the typical case is usually one or two orders of magnitude smaller. Our invention utilizes this fact to reduce the impact of the scheduling latency.

  The Rx buffer overrun problem is dealt with by simply keeping a Rx buffer large enough to handle the worst case interrupt latency. As shown in Figure 2, each time the Rx task is executed, it processes the entire Rx buffer and delivers the decoded data to the upper layer application. Since the application that uses the received data typically has a lower schedul- ing priority as the DSP tasks, this ensures that the Rx task scheduling latency does not increase the delay as seen by the application. As the Rx task can only be blocked by a higher priority level task which would block the execution of the application

0 Motomla, Inc. 1999 1 September 1999

FIELD OF INVENTION

BACKGROUND

  With host processors in personal computers becoming more and more powerful, it becomes fea- sible to implement high speed modems such as ADSL modems in software. However, computation complexity or mips is not the only challenge for a successful implementation of high speed modems. The DSP functions for the high speed modems require real-time execution. However, the host processor may be running many other tasks concur- rently such that its operating system may not be able to guarantee the timely execution of the real-time DSP functions, i.e. there is large response delay. If not being dealt properly, the large response delay can cause transmit buffer underflow and/or receive buffer overflow.

  In addition, the large response time may cause problems for meeting certain requirements. For example, the ADSL standards (G.992.x) requi...