Browse Prior Art Database

TIMER HANDOVER WITH ZERO LATENCY IN A MULTIPROCESSOR SYSTEM

IP.com Disclosure Number: IPCOM000009426D
Original Publication Date: 1999-Sep-01
Included in the Prior Art Database: 2002-Aug-22
Document File: 5 page(s) / 152K

Publishing Venue

Motorola

Related People

Charbel Khawand: AUTHOR

Abstract

Switching PLL off/on to attain a low power mode causes a timer halt in the DSP processor. This time lapse desynchronizes the radio with the system and causes an out of sync condition to occur. Recovering from this case would be as difficult as reacquiring sync with the system similar to a power up state sequence. Since the current consumption in regular wait mode is too high, it is necessary to find a solution to the timer halt during all PLL state tran- sitions.

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Page 1 of 5

MOTOROLA Technical Developments

8

TIMER HANDOVER WITH ZERO LATENCY IN A MULTIPROCESSOR SYSTEM

by Charbel Khawand

STATED PROBLEM

  Switching PLL off/on to attain a low power mode causes a timer halt in the DSP processor. This time lapse desynchronizes the radio with the system and causes an out of sync condition to occur. Recovering from this case would be as difficult as reacquiring sync with the system similar to a power up state sequence. Since the current consumption in regular wait mode is too high, it is necessary to find a solution to the timer halt during all PLL state tran- sitions.

PROBLEM RESOLUTION

  One option would be to maintain power on the timer while the PLL is off but that is not possible for two reasons: High power consumption and/or a change in the silicone. Another viable solution would be for the DSP (high power consumption) to

t

Power Axis

High Pow Mode I I

shut the PLL off during its low power mode, hand- over TDMA timing to the lowest power consuming processor during its PLL switch, and readjust its time when a PLL lock is complete. This publication concentrates on the i,mplementation of such a scheme and on its precision to maintain accurate timing regardless of any handover latencies.

ILLUSTRATION OF THE PROBLEM

  Figure 1 illustrates the problem at hand. The down arrow describes the time during which the DSP is required to slow down its clock to save power. Doing so requires the dsp to quit maintain- ing its channel timing for a small period of time. This is considered an error and if not corrected before the next frame, a channel lost condition takes place. The up arrow is the time the dsp decides to wake up and accelerate its clock. There is also a glitch in time associated with such an operation.

LOW Power Mode

I I I I I I I I b

, Glitch , 1 G'itch 1 DSP Time Axis

Fig. 1

62 Mommla. 1°C. ,999 36 September 1999

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Page 2 of 5

Developments Technicul 0 M MOTOROLA

FIRST SOLUTION WITH LATENCIES

  Figure 2 shows a time inaccurate scheme that handles low power wait modes on the DSP but pays little attention to latencies in the implementation.

  1. The host can only be in wait mode from Tl until TO-Y and cannot be in lpstop.

  2. The DSP must account for the worst message request latency and therefore always be awakened too early which costs current,

ERROR T&T1 is Variable

r

1

Tl I

, Glitch ,

  3. At TO-y the dsp cannot adjust its timer proper- ly due to the unknown variables such as T2-Tl, T3- To+Y and a variable glitch during PLL lock time.

  4. At TO-Y...