Browse Prior Art Database

A VERSATILE APPLICATION BOOTLOAD FOR FIELD PROGRAMMABLE SOC

IP.com Disclosure Number: IPCOM000009445D
Original Publication Date: 1999-Sep-01
Included in the Prior Art Database: 2002-Aug-26
Document File: 3 page(s) / 130K

Publishing Venue

Motorola

Related People

Alan McKenzie: AUTHOR [+4]

Abstract

As silicon technologies improve complete sys- tems on a chip (SoC) are becoming a reality. In addition, the improvement in technology is also dri- ving programmable technologies which can now offer comparable performance and cost to solutions which had been traditionally implemented using gate array technologies. Products are now emerging which can offer the benefits of both high effective gate count, required for SoC; combined with the rapid time to market and prototyping associated with programmable technologies.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 50% of the total text.

Page 1 of 3

Developments Technical 0 M MOTOROLA

A VERSATILE APPLICATION BOOTLOAD

FOR FIELD PROGRAMMABLE SOC

by Alan McKenzie, Roger May, Ed Nuckolls and Bryan Kris

PROBLEM

  As silicon technologies improve complete sys- tems on a chip (SoC) are becoming a reality. In addition, the improvement in technology is also dri- ving programmable technologies which can now offer comparable performance and cost to solutions which had been traditionally implemented using gate array technologies. Products are now emerging which can offer the benefits of both high effective gate count, required for SoC; combined with the rapid time to market and prototyping associated with programmable technologies.

  l Thus a programmable SoC is effectively an inte- grated solution offering a set of custom/semi-custom intellectual (IP) cores which may comprise off microprocessors, peripherals, memory arrays and re- configurable digital and/or analogue arrays.

  Field programmable technologies consist of an array of application re-configurable digital and/or analogue cells which can be implemented on a stan- dard SRAM technology (referred to as FPGA/FPAA technologies, respectively). While an SRAM tech- nology can offer the benefits of high gate density, high performance and fast re-configuration; these benefits are traded against the requirement to have an external application configuration data source which must be loaded into the field programmable configuration memory before application run time, or scheduled for loading within dynamic run-time applications. It is these requirements which are dri- ving the need for a versatile application bootload for field programmable systems on a chip.

SOLUTION

  The solution is to replace the classical dedicated hardware configuration state machine module used within a typical FPGA device with a software

configuration sequencer which executes on the integrated microprocessor core. This solution both limits the hardware overhead of the configuration mechanism, as the microprocessor resources can be re-used at run-time and allows the application con- figuration memory to be distributed throughout the chip, defined by the requirements of the application.

  A typical field programmable SoC is illustrated in Figure 1.

  Distributed application configuration memory may be utilized to configure/program:

   Hardware functionality of the digitahanalogue (FPGA/FPAA) resource.

  l Hardware coefficient look-up tables imple- mented within memory resources embedded within the digitahanalogue programmable ar...