Browse Prior Art Database

LOW COST SINGLE SIDE BAND GENERATOR /IMAGE REJECT MIXER ARCHITECTURES

IP.com Disclosure Number: IPCOM000009471D
Original Publication Date: 1999-Sep-01
Included in the Prior Art Database: 2002-Aug-27
Document File: 3 page(s) / 136K

Publishing Venue

Motorola

Related People

Richard M. Dougherty: AUTHOR

Abstract

Over the last several years the need for improved synthesizer performance has become increasingly acute. In order to enhance perfor- mance, designers have explored the use of adaptive architectures to improve phase noise performance, settling time and spurious generation. In light of this, synthesizer architectures have evolved into mu&loop designs using mixers for signal insertion and spurious frequency dodging.

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MOTOROLA Technical Developments

         LOW COST SINGLE SIDE BAND GENERATOR /IMAGE REJECT MIXER ARCHITECTURES

by Richard M. Dougherty

  Over the last several years the need for improved synthesizer performance has become increasingly acute. In order to enhance perfor- mance, designers have explored the use of adaptive architectures to improve phase noise performance, settling time and spurious generation. In light of this, synthesizer architectures have evolved into mu&loop designs using mixers for signal insertion and spurious frequency dodging.

  Taking this into account, circuit techniques employing Single Side Band Generator (SSBG) / Image Rejection Mixer (IRM) have been embraced to enhance spurious performance. The primary method for spurious improvement using this vehicle is to develop a frequency profile employing a SSBG with the ability to select either upper or lower side- bands to circumvent in band spurious products. The problems normally encountered regarding the afore- mentioned are; complex circuit topologies, limited bandwidth and increased cost/circuit size.

  In consideration of the above, the following addresses and resolves the complexity associated with the formulation of a Single Side Band Generator (SSBG) / IRM architectures used in syn- thesizer designs for frequency control and spurious reduction.

  The need for low cost high performance Single Side Band Generators (SSBG) / IRM in synthesizer applications has become a concern receiving renewed focus with the advent of improved spurious requirements. In addition, focus toward reduced size / cost requires an architecture which can be readily supported by present day ASIC technologies (BICMOS, GCMOS, GaAs . ..etc). The thrust of this article outlines a SSBG architectures, which would address or transcend the following:

l Provide large operational bandwidth

  l Reduce the requirement for high frequency broadband 90 degree hybrids exhibiting excellent phase / amplitude balance

l Improved Image rejection performance

l Provide excellent IF phase I amplitude balance

l Architectures supporting ASIC capabilities

  The principle techniques employed to achieve the aforementioned were:

  1. Employ circuit architectures readily support- ed by ASIC processes (D-or JK Flip Flops, mixers, differential amplifiers, MUX (switches) etc).

  2. Use Low frequency hybrids for the establish- ment I & Q signal.

  3. Utilize Non-reflecting single pole double throw switches (SPDT) for sideband select

  4. Simple 0 degree phase passive combiners (resistive or reactive)

  The approach used to resolve the aforestated, was to formulate architectures using basic mixers structures in conjunction with a simple common RF combing port. In order to select either upper or lower sidebands use was made of a simple non- reflection swit...