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CIRCUIT TO LIMIT DESENSE FROM CMOS DIGITAL ICS

IP.com Disclosure Number: IPCOM000009483D
Original Publication Date: 1999-Sep-01
Included in the Prior Art Database: 2002-Aug-28
Document File: 2 page(s) / 123K

Publishing Venue

Motorola

Related People

Ed Callaway: AUTHOR

Abstract

Desense (receiver interference caused by digital circuit noise) is becoming a greater problem as pagers shrink in physical size and digital circuits move closer to the antenna. (The microprocessor is not more than 1 cm away from the antenna in many modem pager designs.) A major cause of desense is the crowbar, or "shoot-through" current that occurs in digital CMOS gates as they switch. These short, high-amplitude current pulses appear at the IC Vdd and Vss pins, from where they may travel down supply lines, forming current loops that inductively couple into the antenna or other receiver circuits.

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Developments Technical 0 M MOTOROLA

CIRCUIT TO LIMIT DESENSE FROM CMOS DIGITAL ICS

by Ed Callaway

  Desense (receiver interference caused by digital circuit noise) is becoming a greater problem as pagers shrink in physical size and digital circuits move closer to the antenna. (The microprocessor is not more than 1 cm away from the antenna in many modem pager designs.) A major cause of desense is the crowbar, or "shoot-through" current that occurs in digital CMOS gates as they switch. These short, high-amplitude current pulses appear at the IC Vdd and Vss pins, from where they may travel down supply lines, forming current loops that inductively couple into the antenna or other receiver circuits.

  Existing technology places bypass capacitors both internally and externally to "short circuit" the current pulses, minimizing the area of the current loops on the circuit board and so reducing the inter- ference problem. External series inductors may be placed in the supply lines; external transformers are theoretically possible, but they are prohibitively large and expensive in pager applications, although they are widely used elsewhere (e.g., hi-fi audio amplifier power supplies, instrumentation ampli- fiers)

  As the size of the pagers continues to shrink, however, external bypassing is proving to be less and less sufficient. The resulting current loop, even

when an external bypass capacitor is optimally placed, is still large enough to couple to the antenna, and desense remains. External inductors may them- selves inductively couple to other circuits; in any event they are large and a quality problem. Many are wirewound and, when they fail, they fail by cre- ating an open circuit, removing power from the cir- cuit they supply.

  Internal bypassing may be performed, but it is difficult to get sufficient integrated capacitance on the die, due to die size constraints, to support the peak currents required. In many practical cases it seems the current loop on the die itself is of suffr- cient size to couple to other circuits, so no amount of external circuitry will help.

  What is needed is a method of reducing high- frequency current pulses on digital supply lines using only integrated techniques.

  An improved decoupling design uses an inte- grated transformer in the Vdd and Vss supply lines of CMOS digital circuits, to limit high frequency currents. An integrated bypass capacitor improves performance further, by providing a low impedance on-chip between Vdd and Vss. A typical implemen- tation is shown in Figure 1.

Vdd pin

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Circuits

Vss I I pin r-l

Fig. 1

0 MOtornh, 1°C. 1999 131 September 1999

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SUPPlY

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Developments Technical 0 M MOTOROLA

  When switching, crowbar currents from the CMOS...