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STANDARD CELL LIBRARY DESIGNED FOR IDDQ TESTING

IP.com Disclosure Number: IPCOM000009491D
Original Publication Date: 1999-Sep-01
Included in the Prior Art Database: 2002-Aug-28
Document File: 7 page(s) / 287K

Publishing Venue

Motorola

Related People

Paul Riley Crocker: AUTHOR

Abstract

A design methodology for logic is described which provides for the easy application of a voltage across the gate-drain, gate-source, and gate-bulk of all transistors in the circuit. This can be accom- plished in only two test vectors. If the static Idd cur- rent is measured during these two test vectors, the integrity of all gate oxides can be verified. This methodology provides a practical way to do ideal static Idd testing. The penalty for this added testabil- ity is small.

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Developments Technical 0 M MO7-OROL.A

 STANDARD CELL LIBRARY DESIGNED FOR IDDQ TESTING

by Paul Riley Cracker

ABSTRACT static Idd testing. The penalty for this added testabil- ity is small.

  A design methodology for logic is described which provides for the easy application of a voltage BASIC CONCEPT across the gate-drain, gate-source, and gate-bulk of
all transistors in the circuit. This can be accom- If all inputs and all outputs of all the cells of a plished in only two test vectors. If the static Idd cur- design can be forced first to Vdd then to Vss, a volt- rent is measured during these two test vectors, the age across every gate oxide can be achieved. This is integrity of all gate oxides can be verified. This illustrated with the following AND gate example: methodology provides a practical way to do ideal

Inputs and outputs set to Vdd (H) Inputs and outputs set to Vss (L)

  Light shading indicates the transistor has a volt- Note that not all P-N junctions receive the age across the gate oxide to the source, bulk and reversed-bias voltage. Internal nodes within "stacks" drain. Heavy shading indicates a voltage across the of like devices are difficult to test in this way. But it reversed-biased P-N junction. There is some redun- is possible by taking the bulk and well voltages out- dancy where the gate-drain interface may receive side of the normal supply rails during the test. For both voltage polarities, but this is not shown with the example, the P-well voltage would be taken to -lV shading. during the force high test.

0 Motomla,l"c. lW9 1.55 September 1999

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Developments Technical 0 M MOTOROLA =

PRACTICAL IMPLEMENTATION neously forced to either the high or the low state?"

                                This can be answered with the following illustration The first question to ask when evaluating a con- of a typical logic circuit. Within the combinational cent such as this is: "How can the inputs and outputs logic cloud, it can be shown that:
of all the cells in an entire logic section be simulta-

  IF the individual cells are designed such that their outputs are high when their inputs are high,

  AND IF all inputs into this logic cloud are forced high,

  THEN the high state will propagate through every cell to the outputs of the logic cloud.

  The example of the AND gate illustrates that for many cells no extra circuitry is required to ensure that the outputs are high when all the inputs are high. If fact this is true for all non-inverting logic func- tions like AND, OR, AND-OR, etc. Inverting cir- cuits such as INV, NAND, and NOR do require some additional circuitry and some test signal inputs. Details of these cells are shown in the "Example Cells" section.

  All inputs to the combinational logic cloud can be forced high by forcing all the primary inputs to

the logic section high, and by forcing the outputs of all flip-flops high. Similar to the INV, a flip-flop specifically designed for this purp...