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Method for power supply decoupling for 1-mm pitch BGA packaging

IP.com Disclosure Number: IPCOM000009506D
Publication Date: 2002-Aug-28
Document File: 6 page(s) / 312K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for power supply decoupling for 1-mm pitch ball-grid array (BGA) packaging. Benefits include improved performance.

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Method for power supply decoupling for 1-mm pitch BGA packaging

Disclosed is a method for power supply decoupling for 1-mm pitch ball-grid array (BGA) packaging. Benefits include improved performance.

Description

        � � � � � The disclosed method is a set of patterns used in a copper-etch process on a printed circuit board (PCB). The patterns include a ball-grid-to-via configuration and a pattern for populating decoupling capacitors.

        � � � � � For example, the topside of a PCB could contain a pattern for placement and the associated via/trace relationship (see Figure 1). The patter can be expanded and terminated (see Figure 2).

        � � � � � The backside of a PCB could contain a pattern for capacitor pad placement around the via (see Figure 3). The polarity of the via is indicated with the same color as in previous figures. The pattern can be repeated as with previous figures.

� � � � � The number of decoupling capacitors is maximized as the pattern orients them so that no more capacitors could be added without violating manufacturing rules (component keep-outs for registration, see Figure 4). As a result, the most effective use is made of the decoupling area.

        � � � � � The via-to-pad ratio is maximized because a 2‑to‑1 via ratio is maintained by the unique stitching scheme (see Figure 5).

Advantages

        � � � � � The disclosed method provides advantages including:

·        Improved performance due to maximizing the area used for decoupling

·        Improved performance due to maximizing the n...