Browse Prior Art Database

Method for an electronic package assembly carrier that reduces package warpage

IP.com Disclosure Number: IPCOM000009508D
Publication Date: 2002-Aug-28
Document File: 5 page(s) / 79K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for an electronic package assembly carrier that reduces package warpage. Benefits include improved performance.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 50% of the total text.

Method for an electronic package assembly carrier that reduces package warpage

Disclosed is a method for an electronic package assembly carrier that reduces package warpage. Benefits include improved performance.

Background

        � � � � � Thermal interface material (TIM) is a thermally conductive material that is placed between the die and the IHS to improve the thermal resistance between the two components.

        � � � � � Warpage of the package can create many problems for downstream users. For pinned packages, the package warpage contributes to poor pin tip true position, which leads to additional pin rework and potential customer issues. For ball-grid array (BGA) packages, existing JEDEC standards for allowable warpage can be difficult to meet. Excessive warpage on BGA parts can lead to surface-mount issues. For land-grid array (LGA) packages, package warpage can lead to high resistance or open contacts between the package and the socket.

        � � � � � Package warpage can be reduced by reducing the spring force applied to the package during attachment of the integrated heat spreader (IHS). Because the package is supported around its edges during this process, reducing the spring force lowers the bending moment on the package, reducing the warpage. However, reducing the spring force also degrades thermal performance of the package by enabling the bond line of the thermal interface material (TIM) to remain thicker than required, increasing the thermal resistance of the package.

        � � � � � Another option is to accept the additional package warpage, which leads to excessive pin rework, inability to meet JEDEC standards, and marginality in LGA sockets.

        � � � � � In the conventional state-of-the-art carrier, the force applied by the spring clips is not countered at a point opposite the load but by the edges of the package. A large bending movement is generated, causing the package to flex. To cure the TIM, the carrier is processed at elevated temperature, which decreases the strength of the package, enabling it to warp more permanently. The result is a package with the edges warped upward outside the IHS footprint.

        � � � � � Within the pocket of a state of the art carrier, the package is supported by a narrow ledge around the perimeter of the package. This design enables the use of multiple package types in the same carrier, such as packages with no interconnects (see Figure 1), pinned packages (see Figure 2), and packages that have been flipped upside-down for bottom-side processing after the top-side assembly is completed (see Figure 3).

General description

        � � � � � The disclosed method is a metal carrier tray that holds multiple electronic packages while they are being assembled. This carrier incor...