Browse Prior Art Database

Method for a nonstrobe-sensing scheme for SRAM

IP.com Disclosure Number: IPCOM000009516D
Publication Date: 2002-Aug-28
Document File: 8 page(s) / 134K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a nonstrobe-sensing scheme for static random-access memory (SRAM). Benefits include improved performance and improved signal quality.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 46% of the total text.

Method for a nonstrobe-sensing scheme for SRAM

Disclosed is a method for a nonstrobe-sensing scheme for static random-access memory (SRAM). Benefits include improved performance and improved signal quality.

Background

              As bit-line leakage becomes an increasingly severe problem with technology scaling, requirements are identified for sensing schemes that improve regular differential and single-ended sensing in applications such as SRAM.

              Conventional solutions for sensing the bit-line differential voltage in SRAMs include differential sense amplifiers enabled by a strobe signal. Single-ended sensing is conventionally used in register files and SRAMs with short bit-line height. Standard domino circuits are typically used in the single-ended sensing scheme.

              In a typical single-ended sensing scheme, a PMOS transistor is typically used for each bit-line as first-level multiplexing to select a column (see Figure 1). A 4-to-1 multiplexer (MUX) is shown as an example. The first-stage domino sensing circuit is comprised of a precharge (P01), keepers (P02, I1), and highly skewed inverters (P1 and N1, where P1>>N1). The second stage sensing is comprised of keepers (N10, I2), a predischarge device (N11), and a pull-down NMOS N2. The pull-down, N1, in the first stage may not be required if the keeper, P02, is sufficiently large. In a read operation, one of the bit lines is accessed (bit 0). Then BLX is pulled down by the bit-line, if a “0” is being read out. The bit-line and BLX should stay high when a “1” is being read out.

              Note that bit lines (bl0 and bl0#) for each column are present in standard single-ended scheme although only one of them is used.

              Due to increased significant leakage current with technology scaling, the bit-line is pulled-down by leakage current between bit-line and memory cells. A keeper device, P02, is required to stop the leakage and ensure the correct logic operation. However, the presence of P02 slows down the sensing speed when a “0” is being read out because it reduces the effective current (for pulling down the node BLX) from Iread to Iread, I02. The N1 impacts negatively on the sensing speed because the trip point of the inverter (P1 and N1) is lower than Vcc-Vt.

              In the commonly used differential sense amplifier, the strobe signal SA_EN is designed to arrive when bit-line differential has reached a certain target level (see Figure 2). This approach ensures correct evaluation when device mismatch and variations present. The SA_EN signal is designed to have additional margin that guarantees target differential voltage is developed in the worst case (such as among all process corners). The required margin on SA_EN is added on the data latency (SRAM performance) because the sense amplifier cannot resolve until SA_EN occurs.

              As technology scales, the bit-line leakage becomes increasingly significant. The bit-line differential development depends on Ir...