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PCI INTERRUPT ROUTING ENABLES REAL-TIME HIGH PERFORMANCE APPLICATIONS

IP.com Disclosure Number: IPCOM000009538D
Original Publication Date: 1999-Sep-01
Included in the Prior Art Database: 2002-Aug-30
Document File: 3 page(s) / 175K

Publishing Venue

Motorola

Related People

Edoardo Campini: AUTHOR

Abstract

Interrupt processing in current PC1 systems is host centric. This architecture works well in PC systems that have a single processor or processor card. However, this architecture causes problems in embedded real-time systems, as well as multi- processor systems. This paper describes how to improve interrupt processing in PC1 systems.

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MOTOROLA Technical Developments

8

PCI INTERRUPT ROUTING ENABLES REAL-TIME HIGH PERFORMANCE APPLICATIONS

by Edoardo Campini

ABSTRACT

  Interrupt processing in current PC1 systems is host centric. This architecture works well in PC systems that have a single processor or processor card. However, this architecture causes problems in embedded real-time systems, as well as multi- processor systems. This paper describes how to improve interrupt processing in PC1 systems.

PROBLEM WITH EXISTING PCI AND PCI DERIVATIVES

  Current PC1 systems route all of the interrupt signals to the host processor. The PC1 bus is only permitted to have one host processor. This has the implication that the host processor must be involved when handling any interrupt. And therefore, the host is a potential bottleneck and also causes securi- ty violations in secure systems where the host processor may be operating at a different security level than the device which generated the interrupt. Since the PC1 bus has only four interrupt request lines, interrupt service routines often share these lines (interrupt chaining). This has the implication that interrupts are not unique.

  That is, there is now ways to determine who is generating the interrupt by simply inspecting the PC1 interrupt request lines. Hence, an interrupt ser- vice routine must poll its associated device to deter- mine if the interrupt was generated by its corre- sponding device or the device of another interrupt service routine. In cases where the interrupt service routine determines that the interrupt was not gener- ated by its device, it must then chain to another interrupt service routine to let it determine if it should service the interrupt request. This process adds latency to interrupt response. Interrupt latency effects the real-time applications that can be imple- mented with a PC1 system. Interrupt routing solves two PC1 problems:

  1. AI1 interrupts do not always have to be routed to the host processor. Any device can interrupt any other device without the intervention of the host processor. This alleviates host bottleneck and secu- rity issues.

  2. Devices are not required to share interrupt request lines. A unique interrupt vector can be gen- erated by every device so as to not require interrupt chaining, thereby minimizing interrupt latency.

SOLUTION TO PROBLEMS

  An Interrupt Routing circuit can be added to a PC1 backplane to augment the PC1 bus. This circuit can be added in a manner such as to not obsolete existing PC1 devices, yet permit newer devices to take advantage of this feature as required.

METHOD FOR ADDING

INTERRUPT ROUTING TO PCI SYSTEMS

  A fairly simple digital circuit is placed on the PC1 backplane which interrupts the normal signal flow for a subset of the PC1 bus signals between the bus and a PC1 connector. This same circuit is repli- cated for each PC1 connector on the backplane. The Figure 1 illustrates the relationship of this circuit to the PC1 connector and certain PC1 sign...