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MULTIPLE TEST ACCESS PORTS FOR ON-MODULE TESTING OF A SINGLE INTEGRATED CIRCUIT

IP.com Disclosure Number: IPCOM000009545D
Original Publication Date: 1999-Sep-01
Included in the Prior Art Database: 2002-Sep-02
Document File: 2 page(s) / 75K

Publishing Venue

Motorola

Related People

Moshe Solar: AUTHOR [+3]

Abstract

The Joint Test Action Group (JTAG) standard IEEE 1149.1 "Test Access Port and Boundary-Scan Architecture" was developed with the intention to have only a single test access port (TAP) for each integrated circuit (IC). However, it became very common to manufacture KS with multiple TAPS. ICs can be designed to use multiple cores which contain their own TAPS so that a single IC can con- tain core multiple TAPS.

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Developments Technical 0 M MOTOROLA

MULTIPLE TEST ACCESS PORTS FOR ON-MODULE TESTING OF A SINGLE INTEGRATED CIRCUIT

by Avraham Ganor, Moshe Solar and Yoram Yeivin

INTRODUCTION

  The Joint Test Action Group (JTAG) standard IEEE 1149.1 "Test Access Port and Boundary-Scan Architecture" was developed with the intention to have only a single test access port (TAP) for each integrated circuit (IC). However, it became very common to manufacture KS with multiple TAPS. ICs can be designed to use multiple cores which contain their own TAPS so that a single IC can con- tain core multiple TAPS.

PROBLEM

  The standard requires a TAP to provide access for testing the interconnection between KS, within an IC itself and to observe or to modify circuit activ- ity. These functions are available through a bound- ary register. However for an IC with multiple TAPS some problems may occur. For example, a TAP of a core may use special non-standard instructions used to support further functionality trough the JTAG pins. This functionality should be maintained with- out the need to change the core design.

SOLUTION

  The proposed solution is illustrated by an IC having a "SYSTEM TAP" for complete IC and a "CORE TAP" for an embedded core. The expan-

sion by multiple embedded cores is possible. A fist multiplexer alternatively forwards output enable sig- nals from the SYSTEM TAP or from the CORE TAP to an output amplifier providing Test Data Output (TDO) of the IC as a whole; a second multi- plex...