Browse Prior Art Database

CONFIGURATION OF A FIRST-IN-FIRST-OUT (FIFO) FOR USE IN ASYCHRONOUS TRANSFER MODE (ATM)

IP.com Disclosure Number: IPCOM000009565D
Original Publication Date: 1999-Sep-01
Included in the Prior Art Database: 2002-Sep-03
Document File: 3 page(s) / 111K

Publishing Venue

Motorola

Related People

Vadim Vayzer: AUTHOR [+3]

Abstract

This proposal relates to the preliminary storage of data received from serial communication chan- nels by a fast communication controller (FCC).

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MOlOROLA Technical Developments

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 CONFIGURATION OF A FIRST-IN-FIRST-OUT (FIFO) FOR USE IN ASYCHRONOUS TRANSFER MODE (ATM)

by Vadim Vayzer, Eliyahu Shasha and Avi Ganor

  This proposal relates to the preliminary storage of data received from serial communication chan- nels by a fast communication controller (FCC).

  The FCC usually supports a number of commu- nication protocols like HDLC, FNET, ATM and otl- ers. FCC receivers (RX) temporarily store data by relatively large FlFOs. And, this decreases the response time of a reduced instruction set computer (RISC) coupled thereto when the FCC issues a request.

  The read/write address counters of the FIFO point to 256 byte address space. Preferably, the FIFO comprises a DATA FIFO and a STATUS FIFO. Preferably, the DATA FIFO has 16 rows; and each row stores 4 words (4 byte each).

   Fgures l-3 illustrate - by way of example - a pointer generator (for pointers a a a a

0123 =
0000.. ,111 l), the DATA FIFO with the 16 rows (at addresses A&,A,A, = 0000.. 111 l), and a network for transferring pointers a,a,a,a, to addresses

&WY%.

  For convenience, correspondence tables between pointers and addresses are shown left to the figures. For simplicity, addresses A,A, to identify the words within the rows are not further distin- guished.

  The DATA FIFO is partitioned into portions each having 4 rows at consecutive MSB-addresses

A,A, = 00.. 11. The DATA FIFO sometimes stores idles cell which have to be discarded by changing the pointer in short time intervals.

  Figure 1 illustrates a FIFO-configuration with the first 3 portions each storing "large" data cells (64 byte in a cell, Cell Cl at 0000...0011; C2 at OlOO...Olll; and C3 at 1000...1011) addressed according to &A,A,A, = at,a,a,a,.

  Figure 2 illustrates a FIFO-configuration with the first 4 portions each storing "small" data cells (Cl at 0000...0010; C2 at 0100...0110; C3 at
1000...1010; and C4 at 1100...1110) addressed according to AaA,A,A, = aaa,a...