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METHOD AND APPARATUS OF A SYNCHRONIZER CIRCUIT

IP.com Disclosure Number: IPCOM000009569D
Original Publication Date: 1999-Sep-01
Included in the Prior Art Database: 2002-Sep-03
Document File: 8 page(s) / 230K

Publishing Venue

Motorola

Related People

Keith D. Dang: AUTHOR

Abstract

In any asynchronous digital system such as Asynchronous Transfer Mode (ATM) and Asymmetric Digital Subscriber Link (ADSL), the transmitted data from the ATM layer is being cap- tured by the FIFO before allowing the ADSL system to be read. The data rate of the ATM system has a maximum frequency of up to 25 MHz where as the ADSL data rate is at 55.2MHz.

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Page 1 of 8

Technical MOTOROLA @ Developments

 METHOD AND APPARATUS OF A SYNCHRONIZER CIRCUIT

by Keith D. Dang

DESCRIPTION

  In any asynchronous digital system such as Asynchronous Transfer Mode (ATM) and Asymmetric Digital Subscriber Link (ADSL), the transmitted data from the ATM layer is being cap- tured by the FIFO before allowing the ADSL system to be read. The data rate of the ATM system has a maximum frequency of up to 25 MHz where as the ADSL data rate is at 55.2MHz.

  Writing or reading data from the FIFO can be done using dual-port RAM. Since dual-port RAM requires bigger area and consumes more power to operate. It is less likely to be used as efficient solu- tion as compared to single-port RAM. However, if

single-port RAM is the choice, then it would require a synchronizer.

  The purpose of this invention is to demonstrate a method of one would design a synchronize circuit which detects the incoming data from one clock sys- tem to another clock system with a restriction of one clock wide pulse output.

  Figure 1 depicts a block level of a generalized system containing two independent clock signals. System (A) operates on clock signal (ACLK) and System (B) operates on clock signal (BCLK). Data transmitted from system (A) (DIN) passes through the Synchronize Circuit (S) before it is being deliv- ered to system (B).

DIN

SYSTEM SYNCHRONIZE SYSTEM

A CIRCUIT B

>

S

/,

Fig. 1 Generalize system containing two independent clocks.

BCLK

0 Mommla, I".? ,999 269 September 1999

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Developmenls Technical 0 M MO7VROLA

s

  Figure 2 is a circuit diagram of the Synchronize (B). It has two independent clocks ACLK and circuit (S). This circuit is capable of detecting one BCLK, one input data signal DIN and one output or more consecutive pulses from system A and syn- data signal DOUT. The synchronizer contains four chronizing down to one or more pulses (with respect flip-flops, one 3-input AND with two input being to the data DIN signal from system (A) into system inverted, and two 2-input AND gates.

Fig. 2 Synchronizer circuit.

270

q-p& RI'--1 - ~,-3] R'3n

DOUT

September 1999

BCLKB ACLK

DIN BCLK

0 MOmm,a.Inc. ,999

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Page 3 of 8

Developments Technical 0 M MOTOROLA

CIRCUIT OPERATIONS

When the rising edge of ACLK arrives, register FFl

   Assuming the circuit comes out of reset, regis- will detect it on the falling edge of BCLK (BCLKB) ters FFl , FF2, FF3 and FF4 resets to a logic 'OS'. as shown in Figure 3, reference point Ql

ACLK

DIN BCLK

Ql Rl

Q2

R2

Q3

R3 DOUT

Fig. 3 Example when BCLK > = 2 * ACLK

  This signal, Ql , is then ANDed with ACLK clock on the next rising edge of BCLK clock, Q2.

nal, DOUT, forms by ANDing 43 and the input sig- nal DIN and BCLK. This is to guarantee that there

The output of register FF3,43, measures the timing will be only one BCLK clock pulse after the syn- difference between ACLK and BCLK with respect chronization proces...