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IP.com Disclosure Number: IPCOM000009585D
Original Publication Date: 1999-Sep-01
Included in the Prior Art Database: 2002-Sep-04
Document File: 3 page(s) / 157K

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Robert R Fairlie: AUTHOR [+2]


The pipelined data packer described here is a mechanism for grouping packets of digital data each with an indeterminate number of bits into groups of bits of the same size.

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Developments Technical 0 M MOTOROLA


Robert R Fait-lie and Gordon S Allan


  The pipelined data packer described here is a mechanism for grouping packets of digital data each with an indeterminate number of bits into groups of bits of the same size.

  Typical applications include data compression where a compression engine replaces bytes of input data with codes representing sequences of bytes.

  These codes are frequently of variable length and must be 'reconstituted' as a series of regular sized bytes. This technique is known as packing.

  l Consider a data processing system which out- puts quantities of digital data in variable sizes but which needs to pass that data to downstream hard- ware in regular sized amounts (bytes, words etc).

  Such a system may be a data compression engine, which outputs codes of variable size, pass- ing data to a tape drive or other media which deal with data in &bit bytes. The need is to reorganize the stream of data bits output by the system into equal sized quantities to pass on to the downstream hardware.

  Consider as an example a system which outputs a sequence of codes as below...

  This is input to the packer which will conceptu- ally see it as a serial bit stream as below...

 "100100111 101101100110100 01110110010"... which it will divide into 8-bit quantities and pad the final byte with extra OS as below...
. "10010011 11011011 00110100 01110110 OlOOOOW...

and output the following sequence of bytes...

l "10010011" ~"11011011"

l "00110100"

l "01110110"

"0 1000000"

  The ideal situation for the packer is that it output a new byte of data on every clock cycle. This ensures that the packer operates at its maximum throughput and will not constitute a bottleneck in the system.


  One known data compression engine outputs codes whose sizes vary from 9 bits up to 12 bits and which are packed into 8 bit bytes for further pro- cessing downstream. The implementation uses a parallel serial - parallel shift register consisting of 19 bits numbered O-18. Codes are loaded into the shift register in parallel with the code LSB going into bit 7 with increasing order bits going into increasing order locations. Bytes are removed from the register from the bottom 8 bits, O-7. On every clock cycle the register contents are shifted one bit towards the LSB. This register is illustrated in Figure 1.

0 Mommla. 1°C. ,999 305 September 1999

l 9 bit code "100100111"

l 15 bitcode "101101100110100"

l 11 bit code"01110110010"

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Developments Technical 0 M MOTOROLA

byte output by packer




I I I I 0




code input to packer

Fig. 1 Packer Shift Register

  There are two counters associated with the reg- ister of Figure 1. The first is loaded with the length of the code currently being loaded into the counter. It decrements with each clock cycle until it reaches one, whereupon a new code is loaded in...