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Method for a braided wire/elastomer and an apparatus for improved component/motherboard interconnections

IP.com Disclosure Number: IPCOM000009594D
Publication Date: 2002-Sep-04
Document File: 7 page(s) / 242K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed are a method for a braided wire/elastomer and an apparatus for improved component/motherboard interconnections. Benefits include improved power performance and improved reliability.

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Method for a braided wire/elastomer and an apparatus for improved component/motherboard interconnections

Disclosed are a method for a braided wire/elastomer and an apparatus for improved component/motherboard interconnections.� Benefits include improved power performance and improved reliability.

Background

        � � � � � Processor power delivery demands increase with increasing performance. These power delivery requirements can result in high currents flowing through the motherboard to the component. To meet reliability and thermal specifications, this high current often necessitates the use of low resistance board-component interconnects.

        � � � � � One possible solution is to optimize or even remove the socket from the motherboard-to-processor interconnect scheme. Another solution is offering a component that enables the removal or cost reduction of another component in the customer’s assembly bill of materials (BOM).

        � � � � � As silicon technology moves to low K dielectrics, a significant chance for severe coefficient of thermal expansion (CTE) mismatch occurs at the board-to-package interface. This mismatch occurs because packaging materials alter their CTE to better match the fragile dielectric CTE, potentially transferring the mismatch to the board/package interface.

        � � � � � For example, conventional interconnect structures are used for socketed and nonsocketed components. A socket is placed between the component and motherboard to make a nonpermanent electrical connection (see Figure 1). Drawbacks to this assembly include the additional cost and potential performance degradation caused by the socket. Another example is the relative rigidity of the solder ball and the CTE mismatch causing solder-joint failure over the product’s lifetime (see Figure 2). The use of low-CTE packaging materials is expected to exacerbate this problem and complicate the use of socketless processor-attach methods.

General description

        � � � � � The disclosed method is a braided wire/elastomer method and apparatus for improved component-motherboard interconnects. The method simultaneously enables electrical performance gains, improving the CTE-mismatch problem associated with low-K dielectrics.

Advantages

        � � � � � The disclosed method provides advantages, including:

•        � � � � Improved power performance due to a reduction in the number of electrical interfaces from three to two

•        � � � � Improved power performance due to improved contact resistance

•        � � � � Improved reliability due to a more compliant board-component interconnect

•        � � � � Improved ease of manufacturing due to removing the requirements for sockets in system assembly through the use of premounted package contacts and compression mounting

Detailed description

        � � � � � The disclosed method is a braided wire/elastomer method and apparatus for improved component-motherboard interconnects. The method makes use of tooling originally intended for manufacturing braided coaxial cables. The met...