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Programmable Timing Delays for Post-Si Timing Adjustments

IP.com Disclosure Number: IPCOM000009604D
Publication Date: 2002-Sep-04
Document File: 2 page(s) / 43K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a programmable delay element inserted in the paths of clocks that have timing critical design circuits on the clock network. Benefits include cost reductions and a higher yield of manufactured parts.

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Programmable Timing Delays for Post-Si Timing Adjustments

Disclosed is a method for a programmable delay element inserted in the paths of clocks that have timing critical design circuits on the clock network. Benefits include cost reductions and a higher yield of manufactured parts.

General Description

For debug purposes, the disclosed method adds a desired delay to a clock, making necessary setup-hold adjustments. The values are programmed through software (registers) or through straps that are hidden from sight. The delay element is used at the unit/block boundaries, and spare bits from the unit are used to program the delay values.

In a typical application, the disclosed method is used in cross-clock domain circuits (CLK1 runs at faster rate than CLK2). Two programmable delays (PD1, PD2) are inserted in the paths of CLK1 & CLK2. Data from the CLK1 domain is sampled on CLK2. For setup violations CLK2 is delayed, and for hold violations CLK1 is delayed.

Advantages

The following are advantages of the disclosed method:

 

  • Cost reductions by eliminating steps
  • A higher yield of manufactured parts
  • A higher degree of confidence during the design process

Fig. 1

Disclosed anonymously