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Method for interrupt moderation Disclosure Number: IPCOM000009607D
Publication Date: 2002-Sep-04
Document File: 6 page(s) / 128K

Publishing Venue

The Prior Art Database


Disclosed is a method for interrupt moderation. Benefits include improved performance.

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Method for interrupt moderation

Disclosed is a method for interrupt moderation. Benefits include improved performance.


              The goal of any good interrupt moderation scheme is to group the optimal number of interrupt events together and assert the corresponding interrupt with as little latency as possible. This description defines the two criteria used to measure the value of an interrupt moderation scheme, events per interrupt and latency.

              The optimal number of interrupt events (such as received packets) to batch together depends on several factors. As a general rule, as the demand on system resources increases (such as during times of high throughput), the number of events that should be batched together increases so the system can operate efficiently.

              Latency can be measured in several ways. Using the average latency of the packets in a batch, the best possible latency can be calculated as (see Figure 1):

Best case average packet latency = (batch size – 1) / 2

              The latency referred to above is not the latency of the packet transmission or propagation, but a measure of how long the interrupt assertion is delayed. For example, if a batch contains two packets, the first packet is subject to the latency of the second packet’s operation time (transmit or receive) before the interrupt that indicates their presence is asserted. The second packet is not subject to this latency. The result is a best case latency of 0.5 packet times for this bundle. In a batch of four packets, the first packet would be subject to at least three packet-times of latency, the second two packet-times of latency, the third one, and none for the last. Therefore, the average latency of the 4-packet example would be 1.5 packet times (4 -1 / 2).

              I/O controllers can be capable of receiving tens or hundreds of thousands of packets (frames, and cells) per second. Most I/O controllers, such as Ethernet media access controllers (MACs), use interrupts to indicate the arrival of the packets to the device driver, the protocol stack, and applications that need the data.

              In highly pipelined processors, interrupts are inefficient. Generating a high rate of interrupts drastically increases CPU utilization. The system becomes CPU limited and unable to service the received packets. The amount of processing time available is reduced for other parts of the protocol stack, operating system, and applications. Delays can occur in sending acknowledgments. Subsequent packets can be dropped. In the worst case, livelock can occur, reducing the overall throughput and reliability of the system.

              To alleviate this problem, high-speed I/O controllers often implement interrupt moderation. A single interrupt indicates the occurrence of several interrupt events, such as 10 packets being received.

General description

              The disclosed method uses the two interrupt-moderation techniques in a complementary manner. One of the...