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Dynamic Tuning of Control Signals Associated with DRAM Memory Using the End-Point to End-Point Algorithm

IP.com Disclosure Number: IPCOM000009609D
Publication Date: 2002-Sep-04
Document File: 3 page(s) / 91K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that allows the control signals associated with DRAM memory to be dynamically tuned for a variety of silicon and board designs. Benefits include a reduction in errors.

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Dynamic Tuning of Control Signals Associated with DRAM Memory Using the End-Point to End-Point Algorithm

Disclosed is a method that allows the control signals associated with DRAM memory to be dynamically tuned for a variety of silicon and board designs. Benefits include a reduction

in errors.

Background

In current technology, the tuning of various control signals associated with DRAM is done using fixed tables within the firmware. This requires that the firmware be updated periodically to change the tables, based on silicon and board validation discovery. The existing methods occasionally cause errors in the firmware, and require very close interaction between the validation teams and the firmware teams. 

General Description

The disclosed method combines existing silicon features that tune control signals, along with a software algorithm that performs memory operations at various register settings (see Figure 1). The algorithm detects whether the memory write/verify operation passes or fails in order to locate the optimal setting. The algorithm initializes the memory controller tuning registers to the end-point value, then progresses through the available values until the memory write/verify operation passes. It then continues to progress through the remaining settings until the operation begins to fail (see Figure 2). Next, the “pass” value is averaged with the “fail” value, and the average is used as the dynamically determined value that is programmed into the

mem...