Browse Prior Art Database

Method for deadlock escape for complex machines

IP.com Disclosure Number: IPCOM000009614D
Publication Date: 2002-Sep-04
Document File: 2 page(s) / 68K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for deadlock escape for complex machines. Benefits include improved functionality and improved validation and test environments.

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Method for deadlock escape for complex machines

Disclosed is a method for deadlock escape for complex machines. Benefits include improved functionality and improved validation and test environments.

Background

        � � � � � DRAM controller unit (D-unit) services requests from multiple agents to perform read/write accesses to memory. The D-unit also services the Buffer unit (B-unit) for the following requests:

·        CPU

·        Advanced graphics processor

·        Hublink memory accesses

·        Low-priority (LP) graphics agents

·        High-priority (HP) graphics agents

        � � � � � LP streams are relatively ­latency insensitive but have large bandwidth requirements. HP display streams are extremely latency sensitive but have smaller bandwidth requirements. An arbiter in D-unit (DUARB) fairly arbitrates between B-unit and LP streams. B-unit and LP have their corresponding grant counters that indicate the maximum number of grants for each stream in a given arbitration phase. When an HP request or any fixed-priority requests (like page-close and refresh) occur, the fair arbiter goes to a SUSPEND state and services the high priority agents.

        � � � � � The rules for transition from B-unit to LP to SUSPEND are quite complex and require very careful drafting for the elimination of deadlocks. These rules must take into account some static timing constraints that deviate from the otherwise straightforward rules to create more boundary conditions for possible deadlock.

Description

        � � � � � The disclosed method is...