Browse Prior Art Database

A METHOD TO FABRICATE MULTIPLE SEMICONDUCTOR FUNCTIONS ON ONE CHIP

IP.com Disclosure Number: IPCOM000009653D
Original Publication Date: 2000-Jan-01
Included in the Prior Art Database: 2002-Sep-09
Document File: 2 page(s) / 104K

Publishing Venue

Motorola

Related People

H. Ming Liaw: AUTHOR [+3]

Abstract

It is a continuous trend that the IC industry is accelerating the degrees of integration to encompass multi-functional devices in one chip, or so called the system-on-a-chip. The integration of memory func- tion with logic function such as microprocessor has shown great successes. It is anticipated that making a computer in one Si chip can be realized in the near future.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 50% of the total text.

Page 1 of 2

MOlOROLA Technical Developments

A METHOD TO FABRICATE MULTIPLE SEMICONDUCTOR

FUNCTIONS ON ONE CHIP

by H. Ming Liaw, Stella Q. Hong and Syd R. Wilson

BACKGROUND

  It is a continuous trend that the IC industry is accelerating the degrees of integration to encompass multi-functional devices in one chip, or so called the system-on-a-chip. The integration of memory func- tion with logic function such as microprocessor has shown great successes. It is anticipated that making a computer in one Si chip can be realized in the near future.

  The progress on the integration of high frequen- cy (>5 C&z) and/or high power density (>lW/mm) devices with logic devices is lagging behind. Embedding such devices in low power Si logic cir- cuits is difticult due to the following facts: The lack of a suitable electrical isolation for high electric fields between the two functions when a silicon sub- strate is used. The low figure of merits of Si proper- ties for high frequency and high power operation.

SOLUTION TO THE PROBLEM

  We provide a method to enable high power, and/or high frequency RF devices to be integrated in the same chip with low power Si devices. A part of the solution is to replace the Si substrate with a sili- con-on-insulator (SOI) wafer. The SO1 wafer is par- titioned into two parts. One part uses the top Si for fabrication of the low voltage devices for logic cir- cuits. The buried Si02 underneath the top silicon can electrically isolate the logic devices from the sil- icon substrate that forms a conduction path to the high power devices.

  The remaining part of the SO1 wafer is for fabri- cation of power devices. Dielectric walls such as Si02 or Si3N4 are needed to isolate the power from the logic devices. For better heat dissipation, the buried Si02 insulator in this portion of SO1 is not needed. It can be removed together with the top Si

layer and is replaced with another kind of material such as Sic or AlN for a better heat dissipation. The arrangement of the embedded power devices with low voltage devices in a single Si substrate is shown in Figure...