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Method for the selective renaming of 32-bit architecture instructions

IP.com Disclosure Number: IPCOM000009702D
Publication Date: 2002-Sep-11
Document File: 2 page(s) / 51K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for the selective renaming of 32-bit architecture instructions. Benefits include improved performance.

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Method for the selective renaming of 32-bit architecture instructions

Disclosed is a method for the selective renaming of 32-bit architecture instructions. Benefits include improved performance.

Background

        � � � � � In conventional 32-bit architecture, an architectural register consumed by an instruction may have been previously consumed but not modified by another instruction. In this case, the current instruction is required to allocate a new location for the register so the scheduling of other consumers of the register is not hindered.

Description

        � � � � � The disclosed method is a mechanism for selectively renaming 32-bit architecture instructions. If an instruction produces the same architectural register that it consumes and is the sole consumer of that value, its source/destination register is not required to be renamed. Allocation of a physical register is not required by the renamer.

Advantages

        � � � � � The disclosed method provides advantages including:

•        � � � � Reduced number of register allocations

•        � � � � Reduced gate count

•        � � � � Improved power consumption

•        � � � � Reduced lifetime of registers significantly, enabling a machine to have fewer physical registers for any given instruction window and pipeline depth

•        � � � � Wide-processor data locality without scheduler attention

Detailed description

        � � � � � The disclosed method enables a single register consumer to write into the same architectural register.

        � � � � � An exception handler is an implicit consumer of the destination of each register...