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FABRICATION AND STRUCTURE OF A HIGH COMPLIANCE FLIP CHIP INTERCONNECT REWORKABLE FCOB/DCA

IP.com Disclosure Number: IPCOM000009761D
Original Publication Date: 2000-May-01
Included in the Prior Art Database: 2002-Sep-17
Document File: 2 page(s) / 109K

Publishing Venue

Motorola

Related People

Dan Gamota: AUTHOR [+4]

Abstract

A non-underfilled flip chip on board (FCOB) or direct chip attach (DCA) assembly will fail due to the stresses which are generated during the expansion and contraction of the printed wiring board (PWB) during thermal cycling. The generated stress is transferred to the interconnect and a crack is initiated in the interconnect due to fatigue which will ultimately cause the IC to fail during operation. Presently the FCOB rigid interconnect is formed by the reflow of a metallurgical alloy system to connect the die bump (1/0) to a pad located on the PWB.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 50% of the total text.

MOTOROLA

Technical Developments

FABRICATION AND STRUCTURE OF A HIGH COMPLIANCE FLIP CHIP INTERCONNECT REWORKABLE FCOB/DCA

by Dan Gamota, Tom Walsh, George Carson, Cindy Melton and Brian Bullock

A non-underfilled flip chip on board (FCOB) or direct chip attach (DCA) assembly will fail due to the stresses which are generated during the expansion and contraction of the printed wiring board (PWB) during thermal cycling. The generated stress is transferred to the interconnect and a crack is initiated in the interconnect due to fatigue which will ultimately cause the IC to fail during operation.

Presently the FCOB rigid interconnect is formed by the reflow of a metallurgical alloy system to connect the die bump (1/0) to a pad located on the PWB.

The most common die bump metallurgies used today are 97%Pb/3%Sn and 63%Sn/37%Pb. An unencapsulated solder joint composed of these metallurgies will typically fail after 10 cycles of temperature cycling from -SSC to 125C. The previous art disclosed that the reliability perfortnance of a solder joint composed of these metallurgical systems can be enhanced by encapsulating them with a high modulus material. The encapsulant material is dispensed into the gap between the die and PWB.

Computer modeling has shown that the encapsulant reduces the level of stress which is generated and transferred to the interconnects. Historically, a low CTE, high modulus, high T 9 encapsulant composed of an epoxy-based thermoset resin having silica filler is typically used to underfill the die and to constrain the circuit board during thermal cycling.

The underfill couples the die to the PWB and thus, reduces the magnitude of stress transferred to the interconnect and enhances the reliability performance of the FCOB assembly when it is subjected to environmental conditioning.

Unfortunately, the costs, time, and capital required to encapsulate the die is not attractive to a high volume assembly line. The development of a reworkable flip chip assembly structure that does not require encapsulation is very attractive. In addi-

@ Motorola. Inc. 2(XK)

tion, to encapsulation costs, wafer bumping cost will effect the FCOB systems cost and could make FCOB/DCA technology unattractive.

Presently wafers are bumped by electroplating, evaporation or stenciling. Figure 1 is a plot of "different wafer bumping technologies cost per chip" as functions of "1/0 count per chip".

Rela1ive Cost Per Die IS)

1.6

~~Ba"'h Processing CostS ~J---wire bono $S(X)Iwafer - - Ass~.

$liXJIwafer - IM chiplyear

1.4

1.2

1.0

500 d"' ".r wafer ~

----------

100 die per wafer

0.8

0.6 l000djc".rwafer

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