Browse Prior Art Database

A THRESHOLD-SKEWED RAM CELL WITH DEFINED STATE ON POWER-UP

IP.com Disclosure Number: IPCOM000009788D
Original Publication Date: 2000-May-01
Included in the Prior Art Database: 2002-Sep-19
Document File: 3 page(s) / 150K

Publishing Venue

Motorola

Related People

James Smith: AUTHOR [+2]

Abstract

Two TETRA direct mode gateways present on the same direct mode radio communication channel are assigned specific talk-group procedures for use in the case where both gateways are affiliated to the same talk group. Each gateway only attempts to set up a talk-group call after a random period of time, specific to that gateway, has elapsed. If a gateway detects traffic signaling activity during this time then the call set-up message will not be sent.

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MOTOROLA

Technical Developments

A THRESHOLD-SKEWED RAM CELL WITH DEFINED STATE ON POWER-UP

by James Smith and Paul Bonwick

INTRODUCTION

The purpose of this article is to describe a method to solve the problem of random power-up of static ram cells and increase the probability that cells could be made to power-up in a defined state.

The reason the problem exists, the need for a solution, the solution adopted and simulation evidence of the behavior of the cell developed are all described below.

THE CONVENTIONAL SRAM CELL

The conventional SRAM cell which is widely used is based upon 6 transistors and is completely symmetrical and an example of such a cell is depicted in Figure 1.

In this context symmetrical means that each component has a direct counterpart associated with itself on the part of the cell driving the opposite polarity of output and that the device geometries of a given transistor are identical with its counterpart in the same circuit location on the complementary part of the cell.

Thus T 1 matches T2, T3 matches T 4 and T5 matches T6. These components are placed typically in a very tightly packed layout snch that they are in very close proximity to each other.

Thus processing variations are negligible over the short distances of component separation involved and the components can be said to have identical characteristics.

Motorola, Inc. 2000

...

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1'5 1'6 Ti 12

I

1'3

I. .

Fig. 1 Conventional SRAM Cell

This circuit solution for storing data is a very good one because it is based upon connecting two inverters (Tl/T3 being one and T2/T4 being the other) with each output connected to the opposite input and this is an inherently very stable arrangement since it incorporates positive feedback which reinforces the stored state once it has established

However, in a cell with symmetrical components which are matched because of close proximity in the silicon, the initial state of the cell on powerup is truly random and cannot be predicted.

This means that when the cell is powered-up by applying a voltage ramp to Vdd, it is not possible to say in advance which output of b and bbar will be at the high level and which at the low level. It is highly improbable that the cell will sit with each output at the same voltage level for more than a few nanoseconds as with a positive feedback circuit this is a highly unstable region of operation.

82

May 2000

MOTOROLA

Technical Developments

THE PROBLEM REQUIRING A SOLUTION

The SRAM cells were used to hold the configuration for an FPGA (MPA2000) series). In general the output of the circuit was directly attached to the gate of an NMOS transistor (switch). These "switches" defined which nodes were connected together within the FPGA. If the SRAM's were to power up in a random state, a random selection of switches would be turned on. This would lead to bus contentions and a very high current consumption. This could in-mrn lead to latch-up can the destruction of the die.

It was therefore essential to control...