Browse Prior Art Database

DIGITAL FREQUENCY FILTER

IP.com Disclosure Number: IPCOM000009790D
Original Publication Date: 2000-May-01
Included in the Prior Art Database: 2002-Sep-19
Document File: 2 page(s) / 83K

Publishing Venue

Motorola

Related People

Pierre Le Bars: AUTHOR

Abstract

In a mixed analog to digital design, where the digital domain is performing a frequency measurement on a signal that comes from the analog domain, a comparator is required to create the signal for the digital side. In order to avoid false transition coming through to the logic, there is a need for hysteresis around the threshold point in the comparator and filtering of the input signal to avoid false reading the frequency.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 50% of the total text.

MOTOROLA

Technical Developments

DIGITAL FREQUENCY FILTER

by Pierre Le Bars

BACKGROUND

In a mixed analog to digital design, where the digital domain is performing a frequency measurement on a signal that comes from the analog domain, a comparator is required to create the signal for the digital side. In order to avoid false transition coming through to the logic, there is a need for hysteresis around the threshold point in the comparator and filtering of the input signal to avoid false reading the frequency.

PROBLEM

Currently the solution used to avoid false transition when creating the logic signal is to add hysteresis in the analog comparator to avoid false transition around the threshold point that could occur due to noise on the analog signal. This solution is not the most efficient in terms of size and also doesn't provide any flexibility once the design has been created.

SOLUTION

The solution consists in moving the hysteresis detection into the digital domain.

The new concept uses a counter to detect the input signal frequency and subsequently stores the result of the count in a first register. The next measured frequency gives a new value in the counter which is then compared to the previously stored value and if the difference between these two is greater than a predefined percentage it is rejected and a new measurement takes place. This will avoid false detection and therefore remove the need for hysteresis in the analog domain.

The bloc diagram in Figure 1 describes a possible implementation of the system. The state machine will detect the rising (or falling) edges of

Motorola, Inc. 2000

the input signal (named PHASE) and will start and stop the counter when appropriate as well as contr...