Browse Prior Art Database

LONG CODE OFFSET CALCULATION

IP.com Disclosure Number: IPCOM000009795D
Original Publication Date: 2000-May-01
Included in the Prior Art Database: 2002-Sep-19
Document File: 4 page(s) / 145K

Publishing Venue

Motorola

Related People

Steve Price: AUTHOR

Abstract

This idea presents a means of generating offset long code sequences using a minimum of clock cycles.

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This is the abbreviated version, containing approximately 43% of the total text.

MOTOROLA

Technical Developments

LONG CODE OFFSET CALCULATION

by Steve Price

ABSTRACT

This idea presents a means of generating offset long code sequences using a minimum of clock cycles.

INTRODUCTION

This paper describes the equations required to pre-load the quadrature component of the 3GPP long code generator. The equations calculate the equired offset from the values loaded into the X and y registers of the in-phase component.

PROBLEM(S) TO BE SOLVED

The generation of a phase shifted code sequence can take a significant amount of time to clock the generator through the required number of states to reach the final offset. This idea allows the generator to be loaded directly with the offset code, taking only a few clock cycles (the time required to convert the start value into the offset value).

PROPOSED SOLUTION TO THE PROBLEM(S)

A generic linear feedback shift register (LFSR) is shown in Figure I. The shift register is initially loaded with a 'seed' value of ao..an. Each bit of the shift register is fed back into a summing function via a coefficient multiplier which multiplies the bit with one of the coefficients go..gn as shown. The output of the summing function is f(t) (a function of time) which is fed into the left hand side of the shift register. All multiplication and summing operations are binary modulo 2 arithmetic (i.e. f(t) is a I bit value). The shift register is clocked so that each bit moves to the right on each clock edge (i.e. ao moves to the location occupied by a1 and so on). The summer output f(t) is shifted into the input of the shift register, and the right-most bit is taken as the output of the LFSR.

The operation of the LFSR can be written mathematically as shown in equations (I) to (3).

Equation (I) defmes the initial sum value (at t=O).

Equations (2) and (3) define the value of the sum at subsequent times (note that the equations are recursive).

i-O

n

f(O) = Ia; . gj .......................................................................................................................... (1)

I -I n f(tl)=tf(tl-i).g; +La;-ll .g, i-O i:/1

n

f(t2)=Lf(t2 -l-i).gl

j-O

Where O < 11 :$; n ................................................. (2)

Where n < 12 ......................................................(3)

From these equations it can be seen that for any Also, because of the nature of the shift register, given LFSR length (i.e. the value of n), and any set the values of each of the bits in the shift register of coefficients go..gn, f(t) can be calculated to be a (bits O to n) at time t are shown in Figure 2.

fixed function of ao..an.

Motorola. Inc. 2000

103

May 2000

MOTOROLA

Also, because all arithmetic is modulo- 2, use of equations (4) to (6) allows the final equations to be greatly simplified.

xY =x

2n . x = O

(2n + 1) . x = x

From this, the above equations can be entered into any suitable maths package to give the appropriate bit equations after a certain number of clock cycles (value of t). This results in a simpl...