Browse Prior Art Database

Method for Intelligent Command Queuing in Memory

IP.com Disclosure Number: IPCOM000009805D
Publication Date: 2002-Sep-19
Document File: 2 page(s) / 126K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that increases command efficiency for the chipset by intelligently posting commands that adhere to internal command timing requirements. Benefits include better command efficiency and a reduction in latency.

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Method for Intelligent Command Queuing in Memory

Disclosed is a method that increases command efficiency for the chipset by intelligently posting commands that adhere to internal command timing requirements. Benefits include better command efficiency and a reduction in latency.

Background

The rate and efficiency of command delivery to memory affects overall memory performance.  Currently, the chipset issues commands to the memory based on a multitude of timings. Commands issued to memory have to adhere to certain timing parameters, and these can reduce memory efficiency.  For example, Figure 1 shows how the chipset tries to schedule the activate command for a read command it received in T10, but cannot due to the pre-charge already scheduled (commands in white are rank one and commands in gray are rank two). This causes a one clock latency to be added to the read.

General Description

The disclosed method uses intelligent posting for better command efficiency (see Figure 2).

Instead of the chipset, the memory device adheres to the command timing; this allows the chipset to issue all related commands to an operation back-to-back. In Figure 2, the top waveform is the timing on the memory bus interface. The bottom is the internal command timing for each rank; the read command issued to rank two occurs while rank one is doing a pre-charge, allowing a one clock gain on the read latency.

Advantages

Some implementations of the disclosed structure and method provide one or more of th...