Browse Prior Art Database

Method for a simplified DDR memory strobe receiver control mechanism

IP.com Disclosure Number: IPCOM000009808D
Publication Date: 2002-Sep-19
Document File: 5 page(s) / 160K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a simplified double data rate (DDR) memory strobe receiver control mechanism. Benefits include improved performance and improved design simplicity.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 41% of the total text.

Method for a simplified DDR memory strobe receiver control mechanism

Disclosed is a method for a simplified double data rate (DDR) memory strobe receiver control mechanism. Benefits include improved performance and improved design simplicity.

Background

        � � � � � Integrated components that interface with DDR memory are becoming more popular. The first Intel DDR chip was a memory repeater hub (MRH). It was followed by several memory controller hubs (MCH) chips. All of them have been confronted with the same problem. When an MCH or MRH issues a read command to the memory, the hub must wait and ignore data and strobe signals until the memory drives them out of high impedance state.

        � � � � � During this waiting period, data and strobes are not driven by memory, and the MCH/MRH strobe receivers must be turned off. In DDR memory signaling, high-impedance signals are held at the termination voltage, VTT=Vref=VCC/2. Due to noise and uncertainties, high-impedance signals are very likely to be handled by the MCH/MRH as toggling signals.

        � � � � � Conventional designs get around this by sending a signal off chip and reading it back, to guess the latency of the memory. These designs use two pins, traces, and terminations on the board, which increase the overall price of the system.

General description

        � � � � � The disclosed method is a strobe receiver shut-off control mechanism for synchronous dynamic random access memory (SDRAM) and DDR memory busses. The method enables the
strobe receivers when the strobe is no longer in high-impedance but before the strobe starts toggling for data transfers.

        � � � � � For example, an MCH accesses a dual in-line memory module (DIMM) labeled as DIMM#5 for a read command (see Figures 1 and 2). The following steps occur:

1.        � � The MCH core first decides to send a read command

2.        � � The MCH input/output (I/O) buffers drive the command on the command/address bus

3.        � � The DIMM processes the read command and prepares the data

4.        � � The strobe and data are driven by the DIMM on the data/strobe bus

        � � � � � The memory clock is generated by the MCH (see the top waveform of Figure 2) and sent along with the commands to the DIMMs. On the rising edge of the clock, the targeted DIMM recognizes the read command and processes it. The DIMM responds with data after some set amount of time. The delay, channel associated signaling (CAS) latency, is defined in increments of one-half memory clock cycles. One clock cycle before data is sent, the DIMM sets the strobe low. After a flight time delay, the strobe appears low at the MCH as well. At this point, the MCH can safely enable its strobe receivers. It must do so before a full clock period elapses to not miss the first rising edge of the strobe. This window of opportunity is labeled as the Receive enable window.

        � � � � � Ideally, the receive enable window spans over one full clock period. However, accounting for all variations, uncertainties, flight times, and the presence of nume...