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Method for S3 mode on a high-voltage driver using pass-gate isolation

IP.com Disclosure Number: IPCOM000009809D
Publication Date: 2002-Sep-19
Document File: 3 page(s) / 268K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for S3 mode on a high-voltage driver using pass-gate isolation. Benefits include improved power performance.

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Method for S3 mode on a high-voltage driver using pass-gate isolation

Disclosed is a method for S3 mode on a high-voltage driver using pass-gate isolation. Benefits include improved power performance.

Description

        � � � � � The disclosed method is the implementation of an advanced configuration power interface (ACPI) S3 power-save mode in a high-voltage (2.5-V) driver, using a high-voltage control signal. The double data rate (DDR) 266 input/output (I/O) buffer interface in the memory controller hub (MCH) supports ACPI S3 power-save mode. The DDR I/O buffers contain digital circuitry that operate off the core voltage of 1.2V, and predriver/driver circuitry that operate off the 2.5-V supply.

        � � � � � During S3 mode, the 1.2-V supply is shut off, essentially turning off the core. Only the 2.5-V supply remains on. To preserve the data that is in the memory of the DIMMs on the platform, the clock enable (CKE) signal must be driven low before and maintained low through the S3 mode. (see Figure 1) To satisfy this requirement and reduce power consumption in S3 mode, the command/clock buffers are driven low (including CKE), and the data/strobe buffers are tri-stated. The same I/O driver structure is used in all command, clock, data, and strobe buffers in the MCH’s DDR interface.

        � � � � � The following driver structure has two inputs, RESETLOW and RESETHIGHZ, which are expected to be 2.5-V, active-low signals (see Figure 2). This architecture provides the option of either driving low or tri-stating the driver during the power-save mode. If RESETLOW is asserted, the driver outputs low. If RESETHIGHZ is asserted, th...