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Method for DDR memory, dual rail, linearized, and analog compensated on-die bus termination

IP.com Disclosure Number: IPCOM000009812D
Publication Date: 2002-Sep-19
Document File: 6 page(s) / 97K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for double data rate (DDR) memory, dual rail, linearized, and analog compensated on-die bus termination. Benefits include improved performance.

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Method for DDR memory, dual rail, linearized, and analog compensated on-die bus termination

Disclosed is a method for double data rate (DDR) memory, dual rail, linearized, and analog compensated on-die bus termination. Benefits include improved performance.

Background

               A typical conventional four DIMM DDR bus topology (see Figure 1) is comprised of a memory controller hub (MCH) receiver (Rx), a DDR bus, and four dynamic random access memory (DRAM) devices. A typical implementation is to terminate the bus to Vtt through impedance Rt (see Figure 2). Given that Vtt = Vcc/2, Vtt would be required to be on the die for this solution to be successfully implemented. In simulation, this solution demonstrates about 1 Ohm of terminator impedance variation per 100 mV of vbias variation.

              To improve signal integrity, the bus can be terminated at the MCH Rx either on the die or on the printed circuit board (PCB). On-die termination is preferable because it reduces system cost without increasing component cost, and termination can be controlled dynamically. It should be enabled only during memory reads.

 

              Parallel terminators are typically referenced to the bus voltage, Vtt.

General description

              The disclosed method is DDR memory bus termination that enables on-die bus termination (ODT) to a die potential (Vcc) that is twice the maximum bus potential (Vtt, see Figure 3). This approach enables an MCH chip to terminate the DDR bus during memory reads without bringing the midrail termination potential on the die. Pin count and package complexity are reduced.

Advantages

 

              Some implementations of the disclosed structure and method provide one or more of the following advantages:

•             Improved performance due to dynamic control of termination

•             Improved performance due to insensitivity to variations in the compensating bias voltages

•             Improved cost effectiveness due to reduced component count

Detailed description

              The disclosed method is DDR memory ODT. An implementation includes active devices that are compen...