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Method for a PCI bus width detection circuit

IP.com Disclosure Number: IPCOM000009834D
Publication Date: 2002-Sep-20
Document File: 2 page(s) / 33K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a PCI bus width detection circuit. Benefits include improved performance and improved functionality.

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Method for a PCI bus width detection circuit

Disclosed is a method for a PCI bus width detection circuit. Benefits include improved performance and improved functionality.

Description

        � � � � � The disclosed method detects PCI primary bus widths of 32-bit and 64-bit PCI interfaces without the use of a PCI interface protocol or any PCI protocol-related signals. The disclosed method is designed for use in an iSCSI adapter. The circuit utilizes a PCI- to-PCI bridge and a microprocessor. The disclosed method forces the secondary bridge bus width to track with the primary bridge bus width.

        � � � � � The detect circuit is comprised of a resistor pull-up, a common buffer, a tri-state buffer and a 32-bit, high performance I/O chipset with a PCI-to-PCI bridge. The resistor pull-up is attached to an isolated ground pin of the PCI bus interface edge fingers of an iSCSI adapter. GND is isolated from the network interface card’s internal GND and is attached to the input of a common buffer. Its output is attached to the 32-bit enable pin of a tristate buffer. The input of the tristate buffer is tied to GND. The output of the tri-state buffer is tied to a dual-function pin of the I/O chipset. This pin forces the secondary bus of the bridge chip from 32-bit to 64-bit bus widths. At reset, this pin is used as a 32/64-bit bus-width enable. After reset, the pin is used as a data line. If this pin is low after reset, it is deasserted. The secondary PCI bridge bus is forced to 32 bits. If this...