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DYNAMICALLY ADJUSTING THE REFRESH RATE OF SEU SENSITIVE ELEMENTS

IP.com Disclosure Number: IPCOM000009848D
Original Publication Date: 2000-May-01
Included in the Prior Art Database: 2002-Sep-23
Document File: 2 page(s) / 106K

Publishing Venue

Motorola

Related People

Kenneth Wreschner: AUTHOR

Abstract

Recently commercially available extremely dense memory technology is been inserted into space based systems. These next generation systems utilize these highly dense memory devices to develop processor memory elements on the order of many mega bytes. The single event upset (SEU) rate of these memory devices are typically two to three orders of magnitude greater than memory devices which are designed and manufactured on a radiation hardened/SEU tolerant line. As a result, SEU mitigation is required to be designed into these systems to reduce the system impact of upsets.

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MOTOROLA

Technical Developments

DYNAMICALLY ADJUSTING THE REFRESH RATE OF SEU SENSITIVE ELEMENTS

by Kenneth Wreschner

Recently commercially available extremely dense memory technology is been inserted into space based systems. These next generation systems utilize these highly dense memory devices to develop processor memory elements on the order of many mega bytes. The single event upset (SEU) rate of these memory devices are typically two to three orders of magnitude greater than memory devices which are designed and manufactured on a radiation hardened/SEU tolerant line. As a result, SEU mitigation is required to be designed into these systems to reduce the system impact of upsets.

Circuit refreshing is used in these space-based systems to mitigate the SEU rate of the highly dense devices. As an example, memory refreshing is typically performed by an ASIC or state machine in concert with an error correction and detection (EDAC) device. The EDAC is typically capable of double bit detection and single bit correction of memory.

Memory refreshing simply involves sequentially accessing (reading) every location in a memory block. Accessing the memory location will initiate the EDAC to perform bit error detection. If a single bit error is found it can then be corrected before another bit error in that memory location occurs (since double bit errors cannot be corrected).

Depending upon the EDAC and processing architecture, the error correction usually requires additional access time.

Circuit refreshing requires memory access time that could have been used by the processor.

Therefore, hardware designers attempt to minimize the refresh rate to maximize the processing power of the processor. The memory refresh rate (i.e. the rate at which the entire memory block is read and single bit errors corrected) depends upon the SEU rate of the memory devices in the satellite's specific orbit (typically detennined as errorslbit-day). This aver-

Motorola. Inc. 2000

age rate is then multiplied by the number of memory bits to determine a memory block error rate (errors/day). The refresh rate is then typically set to ensure the entire memory is refreshed at a rate greater than the memory block error rate.

During mission operation, the SEU rate is not constant but is primarily a function of orbital location and Sun spot activity. Significant SEU rate changes are therefore observed by Low Earth Orbit satellites. As a result, during periods of high SEU rates, the refres...