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METHOD FOR CONTROLLING CIRCUIT PERFORMANCE OVER VARIATIONS IN PROCESS, VOL TAGE, AND TEMPERATURE

IP.com Disclosure Number: IPCOM000009878D
Original Publication Date: 2000-May-01
Included in the Prior Art Database: 2002-Sep-25
Document File: 2 page(s) / 97K

Publishing Venue

Motorola

Related People

Fujio Takeda: AUTHOR

Abstract

In MOS circuits, propagation delays and MOS FET drive strengths generally varies three to four times over the manufactured process variation (P), operating temperature (T), and power supply voltage Cy). Having less PTV-dependent delay or driver strength circuits are often desirable in many applications. In many cases, it is not an easy task to minimize these variations. For example, IIO designers have been spending a significant amount of time for minimizing simultaneous switching noise, EMC (Electro Magnetic Compatibility), transmission line effect at the best case corner, while meeting propagation delay requirements at the worst case corner.

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MOTOROLA

Technical Developments

METHOD FOR CONTROLLING CIRCUIT PERFORMANCE OVER VARIATIONS IN PROCESS, VOL TAGE, AND TEMPERATURE

by Fujio Takeda

CURRENT PROBLEM

In MOS circuits, propagation delays and MOS FET drive strengths generally varies three to four times over the manufactured process variation (P), operating temperature (T), and power supply voltage Cy). Having less PTV-dependent delay or driver strength circuits are often desirable in many applica.

tions. In many cases, it is not an easy task to minimize these variations. For example, IIO designers have been spending a significant amount of time for minimizing simultaneous switching noise, EMC (Electro Magnetic Compatibility), transmission line effect at the best case corner, while meeting propagation delay requirements at the worst case corner.

Another example is a self timed read trigger circuit in memories, where less PTV-dependent delay circuits are required.

CONVENTIONAL SCHEME

To reduce PTV impact on MOS FET drive strength, insertion of a less PTV~dependent resistor in the drain of MOSFET is one of the most widely used techniques. However, this technique still has a large drive strength variation due to PTV variation unless a large MOS FET is used, which requires a large layout area. Applying a constant current source can be another common approach, but current source circuits are typically quite slow in response and also require large layout area.

NEW SCHEME

The main idea of this scheme is to use a clock as th...