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Method for an electronic packaging substrate with unlanded and/or uncovered vias

IP.com Disclosure Number: IPCOM000009883D
Publication Date: 2002-Sep-25
Document File: 4 page(s) / 64K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for an electronic packaging substrate with unlanded and/or uncovered vias. Benefits include improved power performance and improved design flexibility.

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Method for an electronic packaging substrate with unlanded and/or uncovered vias

Disclosed is a method for an electronic packaging substrate with unlanded and/or uncovered vias. Benefits include improved power performance and improved design flexibility.

Background

        � � � � � Performance of power bus structures (such as package loop inductance) is in part limited by the substrate via pitch. Escape routing of stripline signals is limited by the pad size of via covers and lands. Conventional design rules require that all vias be completely landed on landing pads and covered by cover pads (see Figure 1). Unlanded and uncovered vias would enable tighter pitch.

        � � � � � In the case of laser vias, multiple laser pulses are conventionally required to drill through the overlying dielectric layer. This fact suggests that some number of pulses can clear the overlying dielectric layer but not penetrate all the way through the underlying layer. If the laser does penetrate all the way through, a short may result.�

General description

        � � � � � The disclosed method is an electronic substrate with design rules that explicitly allow vias with bottoms not wholly within a landing pad and tops not wholly covered by a cover pad.

        � � � � � The key elements of the method include:

•        � � � � Processes to enable unlanded and/or uncovered vias with sufficient electrical performance and reliability

•        � � � � Smaller via landing pads and cover pads with the same registration accuracy requirement

Advantages

        � � � � � The disclosed method provides advantages, including:

•        � � � � Improved power performance due to reduced via pitch

•        � � � � Improved design flexibility due to improved stripline escape routing capabilities

Detailed description

        � � � � � The disclosed method is a substrate with unlanded and/or uncovered vias. The landing pads are smaller than the conventional size (see Figure 2). Depending on electrical and reliability requirements, the reduction in landing pad diameter might be as much as the line spacing, approximately from 132 µm to 108 µm.

        � � � � � A via may be partially unlanded (see Figure 3). If photoimageable dielectric material is used, the via does not penetrate into the lower dielectric layer because the material is fully cured.

� � �...