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Method for a substrate top-surface optimizer

IP.com Disclosure Number: IPCOM000009885D
Publication Date: 2002-Sep-25
Document File: 4 page(s) / 1M

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a substrate top-surface optimizer. Benefits include improved performance and improved functionality.

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Method for a substrate top-surface optimizer

Disclosed is a method for a substrate top-surface optimizer. Benefits include improved performance and improved functionality.

Background

        � � � � � Power delivery (PD) requirements are increasingly important. The increasing number of socket pins is accommodated by increasing the size of the package/socket so the power delivery requirement is met and the increased number of input/output (I/O) signals can be completed. Retaining power and I/O access through bottom-side pins results in increased cost.

        � � � � � With the ever-increasing challenges of meeting the load-line characteristics of high performance CPUs, efforts towards achieving better power delivery and I/O performance are evident. Improved PD performance and meeting targeted load lines is achievable by reduced PD path impedance. Some approaches towards reducing the impedance of the power delivery path increase the package size and provide additional power/ground (P/G) pin pairs. This approach is expensive in terms of the material and processes involved and cost. Demand for methods that incur less additional costs is clear.

General description

        � � � � � The disclosed method utilizes the top surface of the package and provides an increased number of power delivery and signal connections. The contribution of motherboard/socket interface parasitic in the PD system is reduced by utilizing the surface area on the top of the package for noncritical I/O signals.

        � � � � � The key elements of the method include:

•� � � � Top surface package connections through pins or lands

•� � � � Improved load line

•� � � � Increased number of signal connections

•� � � � Lower package cost

Advantages

        � � � � � The disclosed method provides advantages, including:

•� � � � Improved power delivery and I/O performance

•� � � � Improved functionality due to improved package size

•� � � � Improved cost effectiveness

Detailed description

        � � � � � The disclosed method enables the use of ~90 power/ground (P/G) pairs by using the package top surface real estate without expanding the package size. With the utilization of a bare-die package, the number can be...